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Explorer
Explorer
270 Views
Registered: ‎04-19-2018

Clocks in device tree

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I've noticed in the device tree files, each node has a 'clock-names' tag, for example:

spi0: spi@ff040000 {
			...
			clock-names = "ref_clk", "pclk";
                        ...
 };

And in the clk-ccf file there are some numbers like:

&spi0 {
	clocks = <&zynqmp_clk 58>, <&zynqmp_clk 31>;
};

But I haven't found neither those clock names or numbers referenced anywhere else, so what's the purpose of this?

 

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Explorer
Explorer
203 Views
Registered: ‎02-22-2012

Re: Clocks in device tree

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Device tree ZynqMP (and Zynq) clock names are connected to Xilinx Linux clocking framework device driver (see Linux kernel sources: drivers/clk/zynqmp/* files).

There is where you will find connections between device tree clock names and clocks in ZynqMP HW.

Linux kernel integrates clocking support (relations, control, ...) via its Common Clk Framework 

Some Xilinx ZynqMP clocking info is also here Common Clock Framework for Zynq Ultrascale+ MPSOC 

WBR Primoz

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3 Replies
Teacher drjohnsmith
Teacher
267 Views
Registered: ‎07-09-2009

Re: Clocks in device tree

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Am I guessing this is the pre configured IP blocks of Xilinx,
In which case, Id not worry, it could be anything from important , in which case dont touch, to redundant "old" code, in which case the tools will ignore ,
If its in the IP, either way , not much you can do about it ,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Explorer
Explorer
248 Views
Registered: ‎04-19-2018

Re: Clocks in device tree

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No, that's in almost all the PS peripherals

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Explorer
Explorer
204 Views
Registered: ‎02-22-2012

Re: Clocks in device tree

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Device tree ZynqMP (and Zynq) clock names are connected to Xilinx Linux clocking framework device driver (see Linux kernel sources: drivers/clk/zynqmp/* files).

There is where you will find connections between device tree clock names and clocks in ZynqMP HW.

Linux kernel integrates clocking support (relations, control, ...) via its Common Clk Framework 

Some Xilinx ZynqMP clocking info is also here Common Clock Framework for Zynq Ultrascale+ MPSOC 

WBR Primoz

View solution in original post