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Adventurer
Adventurer
7,499 Views
Registered: ‎03-23-2015

Compile Uboot for Spartan6 FPGAs

Hi all,

  I just got Uboot working on Microblaze for Spartan6 FPGAs and would like to share my experiences. 

 

Setup:

  Centos 6.7

  ISE 14.7

  Uboot, dtc source as instructed by http://www.wiki.xilinx.com/Build+U-Boot

  Instructions by http://www.wiki.xilinx.com/Build+U-Boot

 

Problem 1:

  If you follow instructions to generate Uboot BSP in SDK, the generated config.mk file will only generate Big Endian executable images.  This is fine if your Microblaze is connected by older PLB bus.  If you are using AXI bus, config.mk must be modified to add compiler and linker flags to instruct Makefile to generate Little Endian Executables.  

  Add to generated config.mk before using to compile uboot.

    PLATFORM_CPPFLAGS += -mlittle-endian
    PLATFORM_CPPFLAGS += -Wl,-mlittle-endian
    PLATFORM_LDFLAGS += -EL

 

Problem 2:

  Instructions to generate Device Tree is left out in the wiki.  But Uboot will still compile using generic (empty) dts such that the output image will reports RAM error when executed.  Somehow console works though.  Xilinx provides BSP to generate device tree but it only works on newer Vivado SDK.

  So I took the HDF file from ISE and imported to Vivado SDK.  Vivado SDK reads and create a new hardware platform without any error.  From here I generated a dts using Xilinx's device tree BSP library.

  But the BSP did not generate entry for a Linear Flash devide that is in the HDF.  Perhaps the IP version is too old and is not detected.  So I created a native Vivado project based on newer 7 Series FPGAs and added microblaze subsystem with linear flash.  When this project is exported to SDK and dts is generated, the linear flash is correctly generated.  This linear flash entry has to be merged into the original dts file for Spartan6 microblaze.  Not many parameters need to be changed for my case as my Spartan6 project is based on SP605 whereas 7series project is based on KC705 and the two seem to share similar flash device.  I only need to change clk_period.

 

  Hope this helps.

 

Regards,

 

Neo

1 Reply
Xilinx Employee
Xilinx Employee
7,259 Views
Registered: ‎07-01-2010

Re: Compile Uboot for Spartan6 FPGAs

@wtneo

 

Appreciate your effort in resolving the issue and sharing the steps to fix the issue.

 

Regards,

Achutha

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