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hcuongvn
Observer
Observer
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Registered: ‎12-21-2011

Creating DDR2 Micorn (MT47H16M16-5E) ((MPMC) IP core in EDK 10.1 failed

I am doing project on board virtex2p, ppc405. I am creating DDR2 (Micorn MT47H16M16-5E) use IP MPMC of Xilinx. I have given and builed success but When I dow file "executable.elf" and Run , the Display:

 

Starting  the Calibration DDR2

 

Erro : Could not calibrate.

1 erro

 

I use source ddr2.c and ddr2.h of Xilinx offers. This is file "powerpc.mhs"


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Thu Aug 23 11:04:11 2012
# Target Board: Custom
# Family: virtex2p
# Device: xc2vp50
# Package: ff1152
# Speed Grade: -7
# Processor: ppc405_0
# Processor clock frequency: 100.00 MHz
# Bus clock frequency: 100.00 MHz
# On Chip Memory : 96 KB
# ##############################################################################
# ##############################################################################
# Template for PPC405 v3 with PLBv46 bus interface
# ##############################################################################
PARAMETER VERSION = 2.1.0


PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT mpmc_0_DDR2_DQS_n = mpmc_0_DDR2_DQS_n, DIR = IO, VEC = [3:0]
PORT mpmc_0_DDR2_DQS = mpmc_0_DDR2_DQS, DIR = IO, VEC = [3:0]
PORT mpmc_0_DDR2_DM_pin = mpmc_0_DDR2_DM, DIR = O, VEC = [3:0]
PORT mpmc_0_DDR2_DQ = mpmc_0_DDR2_DQ, DIR = IO, VEC = [31:0]
PORT mpmc_0_DDR2_Addr_pin = mpmc_0_DDR2_Addr, DIR = O, VEC = [12:0]
PORT mpmc_0_DDR2_BankAddr_pin = mpmc_0_DDR2_BankAddr, DIR = O, VEC = [1:0]
PORT mpmc_0_DDR2_WE_n_pin = mpmc_0_DDR2_WE_n, DIR = O
PORT mpmc_0_DDR2_CAS_n_pin = mpmc_0_DDR2_CAS_n, DIR = O
PORT mpmc_0_DDR2_RAS_n_pin = mpmc_0_DDR2_RAS_n, DIR = O
PORT mpmc_0_DDR2_ODT_pin = mpmc_0_DDR2_ODT, DIR = O, VEC = [0:0]
PORT mpmc_0_DDR2_CS_n_pin = mpmc_0_DDR2_CS_n, DIR = O, VEC = [0:0]
PORT mpmc_0_DDR2_CE_pin = mpmc_0_DDR2_CE, DIR = O, VEC = [0:0]
PORT mpmc_0_DDR2_Clk_n_pin = mpmc_0_DDR2_Clk_n, DIR = O, VEC = [1:0], SIGIS = CLK
PORT mpmc_0_DDR2_Clk_pin = mpmc_0_DDR2_Clk, DIR = O, VEC = [1:0], SIGIS = CLK


BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
BUS_INTERFACE DPLB0 = plb0
BUS_INTERFACE IPLB0 = plb0
BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0
BUS_INTERFACE ISOCM = ppc405_0_iocm
BUS_INTERFACE DSOCM = ppc405_0_docm
BUS_INTERFACE RESETPPC = ppc_reset_bus
PORT BRAMISOCMCLK = sys_clk_s
PORT BRAMDSOCMCLK = sys_clk_s
PORT CPMC405CLOCK = sys_clk_s
END

BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_cntlr_0
PARAMETER HW_VER = 2.01.c
BUS_INTERFACE JTAGPPC0 = jtagppc_cntlr_0_0
END

BEGIN plb_v46
PARAMETER INSTANCE = plb0
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
PARAMETER HW_VER = 1.03.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
PARAMETER INSTANCE = xps_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_SPLB_NATIVE_DWIDTH = 64
PARAMETER C_BASEADDR = 0xffff8000
PARAMETER C_HIGHADDR = 0xffffffff
BUS_INTERFACE SPLB = plb0
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN isocm_v10
PARAMETER INSTANCE = ppc405_0_iocm
PARAMETER HW_VER = 2.00.b
PARAMETER C_ISCNTLVALUE = 0x81
PORT ISOCM_Clk = sys_clk_s
PORT sys_rst = sys_bus_reset
END

BEGIN isbram_if_cntlr
PARAMETER INSTANCE = ppc405_0_iocm_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x44208000
PARAMETER C_HIGHADDR = 0x4420ffff
BUS_INTERFACE ISOCM = ppc405_0_iocm
BUS_INTERFACE DCR_WRITE_PORT = isocm_porta
BUS_INTERFACE INSTRN_READ_PORT = isocm_portb
END

BEGIN bram_block
PARAMETER INSTANCE = isocm_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = isocm_porta
BUS_INTERFACE PORTB = isocm_portb
END

BEGIN dsocm_v10
PARAMETER INSTANCE = ppc405_0_docm
PARAMETER HW_VER = 2.00.b
PARAMETER C_DSCNTLVALUE = 0x81
PORT DSOCM_Clk = sys_clk_s
PORT sys_rst = sys_bus_reset
END

BEGIN dsbram_if_cntlr
PARAMETER INSTANCE = ppc405_0_docm_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0xc2418000
PARAMETER C_HIGHADDR = 0xc241ffff
BUS_INTERFACE DSOCM = ppc405_0_docm
BUS_INTERFACE PORTA = dsocm_porta
END

BEGIN bram_block
PARAMETER INSTANCE = dsocm_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = dsocm_porta
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 125000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = DCM0
PARAMETER C_CLKIN_BUF = FALSE
PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT1_PHASE = 90
PARAMETER C_CLKOUT1_GROUP = DCM0
PARAMETER C_CLKOUT1_BUF = TRUE
PORT CLKOUT0 = sys_clk_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
PORT CLKOUT1 = mpmc_0_MPMC_Clk90
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
BUS_INTERFACE RESETPPC0 = ppc_reset_bus
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
PORT MB_Debug_Sys_Rst = mdm_0_Debug_SYS_Reset
END

BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER HW_VER = 1.00.d
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = plb0
PORT Debug_SYS_Rst = mdm_0_Debug_SYS_Reset
END

BEGIN mpmc
PARAMETER INSTANCE = mpmc_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_MEM_PARTNO = MT47H16M16-5E
PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_MEM_ODT_TYPE = 3
PARAMETER C_MEM_CE_WIDTH = 1
PARAMETER C_MEM_ODT_WIDTH = 1
PARAMETER C_MEM_CLK_WIDTH = 2
PARAMETER C_MEM_CS_N_WIDTH = 1
PARAMETER C_USE_STATIC_PHY = 1
PARAMETER C_MPMC_BASEADDR = 0x00000000
PARAMETER C_MPMC_HIGHADDR = 0x03FFFFFF
PARAMETER C_MPMC_CTRL_BASEADDR = 0x84800000
PARAMETER C_MPMC_CTRL_HIGHADDR = 0x8480ffff
BUS_INTERFACE MPMC_CTRL = plb0
BUS_INTERFACE SPLB0 = plb0
PORT DDR2_DQS_n = mpmc_0_DDR2_DQS_n
PORT DDR2_DQS = mpmc_0_DDR2_DQS
PORT DDR2_DM = mpmc_0_DDR2_DM
PORT DDR2_DQ = mpmc_0_DDR2_DQ
PORT DDR2_Addr = mpmc_0_DDR2_Addr
PORT DDR2_BankAddr = mpmc_0_DDR2_BankAddr
PORT DDR2_WE_n = mpmc_0_DDR2_WE_n
PORT DDR2_CAS_n = mpmc_0_DDR2_CAS_n
PORT DDR2_RAS_n = mpmc_0_DDR2_RAS_n
PORT DDR2_ODT = mpmc_0_DDR2_ODT
PORT DDR2_CS_n = mpmc_0_DDR2_CS_n
PORT DDR2_CE = mpmc_0_DDR2_CE
PORT DDR2_Clk_n = mpmc_0_DDR2_Clk_n
PORT DDR2_Clk = mpmc_0_DDR2_Clk
PORT MPMC_DCM_PSDONE = mpmc_0_MPMC_DCM_PSDONE
PORT MPMC_DCM_PSINCDEC = mpmc_0_MPMC_DCM_PSINCDEC
PORT MPMC_DCM_PSEN = mpmc_0_MPMC_DCM_PSEN
PORT MPMC_Clk_Mem = mpmc_0_MPMC_Clk_Mem
PORT MPMC_Rst = sys_periph_reset
PORT MPMC_Clk90 = mpmc_0_MPMC_Clk90
PORT MPMC_Clk0 = sys_clk_s
END

BEGIN dcm_module
PARAMETER INSTANCE = dcm_module_0
PARAMETER HW_VER = 1.00.d
PARAMETER C_CLKOUT_PHASE_SHIFT = VARIABLE
PARAMETER C_CLKIN_PERIOD = 10.000
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_CLK0_BUF = TRUE
PORT PSDONE = mpmc_0_MPMC_DCM_PSDONE
PORT CLK0 = mpmc_0_MPMC_Clk_Mem
PORT PSINCDEC = mpmc_0_MPMC_DCM_PSINCDEC
PORT PSEN = mpmc_0_MPMC_DCM_PSEN
PORT CLKFB = mpmc_0_MPMC_Clk_Mem
PORT RST = sys_rst_s
PORT PSCLK = sys_clk_s
PORT CLKIN = sys_clk_s
END

 

Everybody can help me. I want to ask you advice as to what direction should I go to solve this problem.

 

Thanks very much.!!

 

 

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