10-14-2009 12:42 PM
I can't seem to find much in way of examples, so I'll ask here. I want to take control of many of the GPIOs of the PowerPC on my Virtex 5, at high speeds. I'm using the latest kernel from the GIT server, and ELDK to compile.
I realize this will end up with me writing a module, but for now I was going to try and use the GPIO framework for testing at lower toggle speeds. I have the LEDs working through the kernel's GPIO structure, and want to expand on that. My board is an Avnet V5FXT Evaluation kit.
My question is this. I've added in a new instance of the xps_gpio ip core to my XPS project, and have set it to 32 bits (the size I need). Where do I go from here, as far as setting how this GPIO core is tied to specific pins on the processor. I think it will have something to do with the Base Address and the High Address, but I'm not 100%.
I read all of the GPIO documentation on the xilinx wikidot. It was very informative and helped me get control of my LEDs. I can't seem to find much on creating custom GPIO devices and using specific pins/ports, however.
Thanks a lot for the help,
10-15-2009 08:20 AM
The IO's are all programmable (except for a very few dedicated pins for configuration).
The PPC does not connect to anything, unless you program the FPGA to do so.
So, your question does not make any sense to me, except for the part about not finding any examples.
I suggest you go look at the ML50X series pcbs, and all of the support information, and download the designs, and run the designs in the tools, to see how things get done.
10-16-2009 11:26 AM
I'm sorry, I'm new to this technology and have a bad habit of using the wrong terminology. When I said pins on the processor, I meant the FPGA. I realize the PPC I/Os are not tied to anything on the FPGA until a design is made, and that's where I'm stuck.
I want to take control of specific pins on the FPGA (Such as the ones ties to the SAM port of my dev kit, and many of the connections on my expansion mezzanine connector) as GPIOs from the kernel. I assume this involves programming the FPGA to link the correct pins and lines from my board to I/Os on the PPC. Then get the kernel to recognize the correct I/Os as a GPIO device, and take control that way.
I think this is the correct method, though I have no idea how to go about doing it. I will definitely take a look at the link and designs you offered, though.
Thanks for the help.
10-16-2009 11:36 AM
VHDL, or verilog, which are hardware description languages (HDL), are used to develop the design for the FPGA.
At the hardware level, you must specify the pin, the standard, and the logical function that gets connected.
The IO standards may be specified in a constrain file (.ucf), or directly in the HDL code.
ISE Logic Editon is the logic platform which supports this activity.
ISE Embedded Edition is the platform for integrating the hardware, with the software. It also creates constraint files (.ucf) based on files you create to specify the IO connections and standards.
What you are describing is how to specify and modify the hardware interface for your embedded system.
You may either use the "free IP" provided by the Embedded tool to design a system from pre-existing blocks (processors, memory controllers, timer/counters, interrupt controllers, bus interfaces, etc.) and constrain the design to assign these blocks external interfaces to pins on the package, and specify the IO standards, or, you need to write your own HDL (verilog or VHDL) to create your own blocks to be added to the Embedded Edition project.