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jdefields
Explorer
Explorer
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Registered: ‎12-02-2014

Custom Zynqmp Board - Hangs at BSS register access

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We've got our hands on our first zynqmp custom board!

 

We're encountering an issue where the first time we attempt to access a statically defined variable/struct ('fat_registered' in spl_fat.c), the system hangs with no obvious error or console output.  I can see from u-boot-spl.map, that 'fat_registered' is the first .bss variable @0x00000000.  Bypassing this access or moving the register outside of the BSS with static int fat_registered __section(".data"),  the system fails on the next statically declared structure.  If I move all of those static structures outside of BSS, I'll get the following output:

 

U-Boot SPL 2017.01 (Jun 30 2017 - 10:58:11)
EL Level: EL3
Trying to boot from MMC1
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1
spl: no partition table found
spl: no partition table found
SPL: failed to boot from all boot devices

 

I'm guessing we have some memory configuration issue.  I have confirmed that the DDRC and DDR Phy registers match the zcu102 (with the exception of timing information and bank setup).

 

We have a single bank setup:

memory {

                device_type = "memory";

                reg = <0x0 0x0 0x0 0x80000000>;

};

 

I've set: #define CONFIG_NR_DRAM_BANKS     1

 

Everything else is basically the same as zcu102 eval board.

 

Any ideas?

 

Justin D.

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jdefields
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Explorer
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Registered: ‎12-02-2014

Issue with .BSS variables ended up being unstable DDR4 settings.  Had to lower speed / loosen timings.

 

Issue with MMC seems to be due to incorrectly setup (or unstable) shdci interface.  Lowering the SD1 bus speed manually to 12.5MHz allowed the unit to boot to uboot full.

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jdefields
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Registered: ‎12-02-2014

For comparison:

 

ZCU102:

U-Boot SPL 2017.01 (Jun 27 2017 - 16:44:18)
ddrc_mstr (0xfd070000) = 0x41040010
ddrc_stat (0xfd070004) = 0x1
ddrc_mrctrl0 (0xfd070010) = 0x30
ddr_phy_pir (0xfd080004) = 0x0
ddr_psgr0 (0xfd080030) = 0x80004fff
ddr_zq0sr (0xfd08069c) = 0x200
ddr_zq1sr (0xfd0806bc) = 0x200

 

Custom Board:

U-Boot SPL 2017.01 (Jun 29 2017 - 09:23:15)

ddrc_mstr    (0xfd070000) = 0x81040010

ddrc_stat    (0xfd070004) = 0x1

ddrc_mrctrl0 (0xfd070010) = 0x6010

ddr_phy_pir  (0xfd080004) = 0x0

ddr_psgr0    (0xfd080030) = 0x80004fff

ddr_zq0sr    (0xfd08069c) = 0x200

ddr_zq1sr    (0xfd0806bc) = 0x200

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jdefields
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Explorer
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Registered: ‎12-02-2014

Issue with .BSS variables ended up being unstable DDR4 settings.  Had to lower speed / loosen timings.

 

Issue with MMC seems to be due to incorrectly setup (or unstable) shdci interface.  Lowering the SD1 bus speed manually to 12.5MHz allowed the unit to boot to uboot full.

View solution in original post

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