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Registered: ‎01-20-2019

DP Display - pll lock failed | MPSoC device

Dear all,

I hope all are doing great.

I am having the problem to enable the DP display interface on my custom MPSoC device. I have build the project with the following project configuration.

Environment:

Xilinx Vivado 2019.2

Xilinx petaLinux 2019.2

Vivado DP configuration 

     dp-port.png

 

dp-ref_clk.png

 

 

Petalinux configuration

Kernel Configuration:

CONFIG_XILINX_DPDMA=y
CONFIG_CMA=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=256

CONFIG_DRM_XLNX=y
CONFIG_DRM_XLNX_BRIDGE=y
CONFIG_DRM_XLNX_BRIDGE_DEBUG_FS=y
CONFIG_DRM_ZYNQMP_DPSUB=y

Reference link:- 

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842105/ZynqMP+DisplayPort+Linux+driver

 

system-user.dtsi

&zynqmp_dpsub {
phy-names = "dp-phy0","dp-phy1";
phys = <&lane1 6 0 1 27000000>, <&lane0 6 1 1 27000000>;
status = "okay";
xlnx,max-lanes = <2>;
};

&xlnx_dpdma {
status = "okay";
};

Problem

while booting the board I can see that DP port configuration is failing with the below log. 

[ 4.341781] xilinx-psgtr fd400000.zynqmp_phy: PLL lock time out
[ 4.347703] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:no
[ 4.355443] zynqmp-display fd4a0000.zynqmp-display: failed to lock pll
[ 4.361982] zynqmp-display: probe of fd4a0000.zynqmp-display failed with error -110

It will be highly appreciated if anyone could help to address this issue?

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Registered: ‎01-20-2019

Re: DP Display - pll lock failed | MPSoC device

does anybody have any suggestions on this issue?

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Registered: ‎01-20-2019

Re: DP Display - pll lock failed | MPSoC device

Hi all,

Can anyone help me to work around the above issue?

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Registered: ‎06-16-2013

Re: DP Display - pll lock failed | MPSoC device

Hi @deepg799 

 

Where is your video source ?

Did you make sure whether video source is proper or not ?

Refer the following document.

 

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf#page=958

 

Best regards,

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Registered: ‎01-20-2019

Re: DP Display - pll lock failed | MPSoC device

Hi @watari 

Thanks for the update.

Yes, I make sure that my video source (DP monitor) is coming connected properly.

In the booting log I can see the error message shown below:

[15.100543] xilinx-psgtr fd400000.zynqmp_phy: PLL lock time out
[15.100543] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:no
[15.108284] zynqmp-display fd4a0000.zynqmp_phy: PLL lock time out
[15.114824] zynqmp-display: probe of fd4a0000.zynqmp-display failed with error -110

The same petalinux and vivado configuration is working fine in 2018.3 tool version.

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Registered: ‎06-16-2013

Re: DP Display - pll lock failed | MPSoC device

Hi @deepg799 

 

>Yes, I make sure that my video source (DP monitor) is coming connected properly.

 

No. DP monitor is sink device. I ask you where is your video source module to make sure connection and so on in MPSoC ?

ex. Your own designed VTC with video signal and it goes out through dp live video...

 

>[15.100543] xilinx-psgtr fd400000.zynqmp_phy: PLL lock time out
>[15.100543] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:no
>[15.108284] zynqmp-display fd4a0000.zynqmp_phy: PLL lock time out
>[15.114824] zynqmp-display: probe of fd4a0000.zynqmp-display failed with error -110

 

Would you make sure source clock setting to this PLL and connection to zynqmp_phy, too ?

 

Best regards,

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Registered: ‎01-20-2019

Re: DP Display - pll lock failed | MPSoC device

Hi @watari 

Thanks for the update.

here nothing is involved in PL side related to DP source. We are testing the PS DP interface.

Below is the screenshot for the output clock configuration, and you can also find the I/P clock configuration as shown above diagram. 

The same i/p and o/p clock configuration I made in 2018.3 and it is working fine. please let me know if I missed any information here.

 

 

output_clk.png

 

Thank you in advance

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Registered: ‎01-20-2019

Re: DP Display - pll lock failed | MPSoC device

@watari 

For your reference also attaching the vivado BD design. 

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Registered: ‎06-16-2013

Re: DP Display - pll lock failed | MPSoC device

Hi @deepg799 

 

I confirmed boot log file and bd file and so on.

It seems wrong clock setting in dtb file.

Would you make sure device tree or share it ?

 

Best regards,

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Registered: ‎01-20-2019

Re: DP Display - pll lock failed | MPSoC device

Hi @watari 

Attaching the system.dtsi, pcw.dtsi and system.dts file

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Registered: ‎01-20-2019

Re: DP Display - pll lock failed | MPSoC device

Hi @watari 

Yes, I think you are right it is a problem with device tree configuration. because I removed the device tree from the working project and I met with the same error. That means In this project also device tree is not configured properly.

Could you please guide me to configure it properly?

Thanks in advance.

 

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Registered: ‎06-16-2013

Re: DP Display - pll lock failed | MPSoC device

Hi @deepg799 

 

Would you make sure connection and parameter abbout dp_vtc_pixel_clk_in ?

Unfortunately since I didn't have enough information about your design, I couldn't investigate the route cause.

But I suspect "dp_vtc_pixel_clk_in".

 

Best regards,

 

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