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Registered: ‎05-23-2018

DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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Hi,

We're trying to build a design based on the Video Codec Unit Targeted Reference Design with slight modifications in the video pipeline. We're trying to connect our own IP:s in the middle of the video pipeline, more precicely between the AXIS register slice block and Video Frame Buffer Write in the HDMI input group. However, this seems to break the device tree generation TCL scripts (here https://github.com/Xilinx/device-tree-xlnx/blob/master/vproc_ss/data/vproc_ss.tcl#L142-L143) since it does not recognize the receiving IP block that the AXIS register slice block is connected to.

Here is the relevant part of the error log (the full log is attached):

| ERROR: [Common 17-161] Invalid option value '' specified for 'object'.
| ERROR: [Hsi 55-1545] Problem running tcl command ::sw_vproc_ss::generate : ERROR: [Common 17-161] Invalid option value '' specified for 'object'.
| 
|     while executing
| "get_property IP_NAME $axis_reg_slice_ip"
|     (procedure "::sw_vproc_ss::generate" line 111)
|     invoked from within
| "::sw_vproc_ss::generate HDMI_RX_PRE_v_proc_ss_0"
| ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
| hsi::generate_target: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 822.945 ; gain = 15.438 ; free physical = 296 ; free virtual = 27335
| generate_target failed
|     while executing
| "error "generate_target failed""
|     invoked from within
| "if {[catch {hsi generate_target -dir $project} res]} {
|   error "generate_target failed"
| }"
|     (file "/build/tmp/work/plnx_zynqmp-xilinx-linux/device-tree/xilinx+gitAUTOINC+b7466bbeee-r0/dtgen.tcl" line 38)

How can we work around said issue? Is it possible to use the DTG with a partly modified video pipeline? If not, can we write our own device tree and specify Petalinux to use it instead?

The corresponding HDF is attached.

Best regards,
Erasmus Cedernaes

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Registered: ‎09-12-2007

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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I took a look at this today. This is a bug in the DTG in the v_proc_ss tcl (as I dont believe the DTG should ever crash even if it is not provided the expected info.. more on that later)

If we look at the section that is failing based on your error msg:

block.PNG

Here, we see the v_proc_ss, connected to a broadcaster, then axis_slice, but then connected external to the Block design.

The XSA only contains IP in the BD. The DTG is trying to establish the video pipeline:

 

For exaple, we can track this by adding prints along the pipeline.

debug.PNG

 

So, as you can see here, the command to get the stream IP connected to the axi register slice fails (as it is made external)

 

So, technically this is a bug IMO (the DTG shouldnt crash). To patch this, I just added a condition on the axis_reg_slice_ip to make sure it was not blank, and suppressed this as a warning to allow the DTG to continue:

warning.PNG

However, since the DTG is missing the pipeline info, you will need to add this manually to the devicetree.

My patch for 2019.2 is attached. To use this in Petalinux, then see the wiki below:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/136904764/Creating+Devicetree+from+Devicetree+Generator+for+Zynq+Ultrascale+and+Zynq+7000

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Registered: ‎11-09-2015

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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Hi @erasmus.cedernaes.saab 

Is it possible for you to move your project to 2019.2? There were some fixes to the device tree thus it might not crash. But with that say it will still not generate the entry for your IP.

If it is still failing can you share the xsa (replace HDF in 2019.2) and I will have a look?

And yes, you can write your own device tree. If you just need to add entries to the device tree generated by petalunux (when it does not crash as in your case) you can use the system-user.dtsi file.

When you need to add you full device tree you can use the option --dtb in petalinux package


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎05-23-2018

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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Hi @florentw,

Thank you for the quick answer!
We will port the project to 2019.2 and see if that fixes it and otherwise try the other alternatives that you listed. I will come back with our results.

Best regards,
Erasmus

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Registered: ‎09-12-2007

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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I tried your HW in the latest version of the DTG and I see the same issue. So, I suspect you will see this too even if you port to 2019.2.

I tried to open your HW but failed as there are custom HDMI cores here. If you like you can send these to me via PM and I can debug and patch the DTG for you.

 

 

 

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Registered: ‎03-21-2019

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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Here are some links to related topics:

https://forums.xilinx.com/t5/Embedded-Development-Tools/2018-3-Zynq-UltraScale-MPSoC-DTG-fails-to-generates-the-nodes/m-p/1062718#M51832

https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-v2019-1-device-tree-xilinx-build-fails-at-do-configure/m-p/1026145/highlight/false#M36884

https://www.xilinx.com/support/answers/72366.html

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/128024605/DTG+limitation+for+multimedia+IPs

 

None of these directly solved my problem, but I have an open SR with Xilinx about the issue.

Basically, DTG can't handle multiple video pipelines in a design. If you are in a Petalinux version prior to 2019.2, you will see build errors because of this. A patch, such as one of the ones from those other forum posts, can turn the errors into warnings, which will let you complete the build. However, the resulting device tree will still be incorrect. You need to manually fix the device tree by modying system-user.dtsi (or similar.)

Also, none of those patches worked for me until I modified them to suit my project. You may need to do the same. Luckily for you, it sounds like Stephen is on the case.

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Registered: ‎09-12-2007

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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Hey @eliezer , if y ou want me to take a look at your issue  you can post your HDF here. 

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Registered: ‎03-21-2019

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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Thank you for the kind offer, Stephen, but Kunal is already working on it in my SR. He already has the HDF, device tree, log files, etc., so hopefully he can solve it for me.

If you have a good tutorial or document that explains how to fix the device tree in this circumstance, that would be very much appreciated, however. I may need to fix the device tree for a large number of different hardware designs, and I can't send them all to Kunal, so I would like to have a good work flow for fixing device trees in general.

So far, the closest thing I have found is the examples provided in this document on the wiki. 

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Registered: ‎05-23-2018

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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Hi @stephenm,

Here is the full project for Vivado 2019.2.
Unzip it, go to the folder `2019-2-tcl/` and source the `vcu_trd.tcl` script in Vivado.

Best regards,
Erasmus Cedernaes

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Registered: ‎05-23-2018

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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I think I forgot to attach the file :)

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Moderator
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Registered: ‎09-12-2007

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

Jump to solution

I took a look at this today. This is a bug in the DTG in the v_proc_ss tcl (as I dont believe the DTG should ever crash even if it is not provided the expected info.. more on that later)

If we look at the section that is failing based on your error msg:

block.PNG

Here, we see the v_proc_ss, connected to a broadcaster, then axis_slice, but then connected external to the Block design.

The XSA only contains IP in the BD. The DTG is trying to establish the video pipeline:

 

For exaple, we can track this by adding prints along the pipeline.

debug.PNG

 

So, as you can see here, the command to get the stream IP connected to the axi register slice fails (as it is made external)

 

So, technically this is a bug IMO (the DTG shouldnt crash). To patch this, I just added a condition on the axis_reg_slice_ip to make sure it was not blank, and suppressed this as a warning to allow the DTG to continue:

warning.PNG

However, since the DTG is missing the pipeline info, you will need to add this manually to the devicetree.

My patch for 2019.2 is attached. To use this in Petalinux, then see the wiki below:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/136904764/Creating+Devicetree+from+Devicetree+Generator+for+Zynq+Ultrascale+and+Zynq+7000

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Registered: ‎05-23-2018

Re: DTG fails when modifying video pipeline in VCU TRD blockdesign (Petalinux 2018.3)

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Hi @stephenm,

This solves the problem of the DTG crashing. Thanks for the help!

Best regards,
Erasmus Cedernaes

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