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Contributor
Contributor
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Registered: ‎05-09-2018

DTS for MAC/PHY for PCS/PMA/SGMII

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I looked at many different examples, including xapp1305, in order to determine the correct DTS snippet to put in system-user.dtsi but I can't seem to make Linux happy.  U-boot says the IF gets an IP address and I'm able to ping the host PC from my target, but not vice versa (unless I initiate a ping from target side simultaneously).  Regardless when the kernel is booting I see: Configuring network interfaces... Cannot find device "eth0" and this from the macb driver:  macb ff0b0000.ethernet: Not enabling partial store and forward.  My target is a custom zynqMP board w/ TI83867ISRGZ PHY.  We're connecting PS GEM0 to a PCS/PMA or SGMII IP block.  I've read many similar posts and have tried many variations of DTS snippets; this is what I'm currently trying:

&gem0 {
     phy-mode = "sgmii";
     phy-handle = <&phy0>;
     mdio {
          #address-cells = <1>;
          #size-cells = <0>;
          phy0: phy@0 {
                reg = <0x0>;
                xlnx,phy-type = <0x4>;
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
                ti,rxctrl-strap-worka;
          };

      };

};

And here are some of the other settings I've tried:

/* try #1 */
/*
&gem0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii";
phy0: phy@0{
reg = <0>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
};
*/

/* try #2 */
/*
&gem0 {
compatible = "cdns,zynqmp-gem";
status = "okay"
local-mac-address = [00 0a 35 00 22 01];
phy-mode = "sgmii";
phy-connection-type = "sgmii";
phy-handle = <&phy0>;

mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
status = "okay";
reg = <0x0>;
xlnx,phy-type = <0x4>;
};
};
};
*/

/* try #3 */
/*
ethernet_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy@1 {
compatible = "Xilinx PCS/PMA PHY";
device_type = "ethernet-phy";
reg = <1>;
};
*/

/* try #4 */
/*
&gem0 {
compatible = "cdns,zynqmp-gem";
status = "okay";
local-mac-address = [00 0a 35 00 22 01];
phy-mode = "sgmii";
phy-handle = <&phy0>;

mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
compatible = "Xilinx PCS/PMA PHY";
device_type = "ethernet-phy";
status = "okay";
reg = <0x0>;
xlnx,phy-type = <0x4>;
};
};
};
*/

We were able to run the LwIP baremetal example (xapp1306) on our board I so don't think its a HW or FPGA design problem.  I'm not sure if there's some other options in the kernel I need to enable/disable or I haven't found the correct DTS snippet for our FPGA design (see attached).

Screenshot from 2019-05-14 16-09-34.png
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Contributor
Contributor
195 Views
Registered: ‎05-09-2018

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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I probably had the GEM node correct for sometime.  Turns out the issue wasn't with the DT... kind of.  We have a AXI GPIO block in our design that takes the extenal clock generator (for the SGMII bridge) out of reset.  Although we were configuring the AXI GPIO block in the FSBL, Linux, at power-up, apparently writes to the AXI GPIO block to set the outputs to their default state; in our case, the default value (0x00) holds the SMII bridge in reset. :/

The is what I used for the GEM node; reading through the MACB driver, I understand that having a MDIO bus under the GEM is optional, so is the status property.  IMO reading through the driver was the best way to verify the DT node was correct.

&gem0 {
    phy-handle = <&phy9>;
    phy9: phy@9 {
        reg = <0x9>;
        xlnx,phy-type = <0x4>;
    };
};

To change the default value for Linux, I modified the AXI GPIO node with:

&axi_gpio_0 {
    xlnx,dout-default = <0x0002000F>;
    xlnx,dout-default-2 = <0x0>;
};

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Xilinx Employee
Xilinx Employee
372 Views
Registered: ‎04-15-2011

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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@malburgj 

 Linux can manage only one phy through MDIO with phy-handle setting in device tree. There are two phys in your system. 

In the two phys system, we can assign external phy node to phy-handle, and let linux manage external phy device. We can manually remove pcs-pma phy isolation with configuration_vector and configuration_valid port. For more details, refer to PG047.

And don't set " phy-mode = "sgmii" " in Gem node, because Gem driver will enable pcs and sgmii configuration inside PS, and gmii interface won't connect with EMIO. Set phy-mode to gmii instead.

 

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Contributor
Contributor
361 Views
Registered: ‎05-09-2018

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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@longley thank you for the reply.

I'm currently using the DTS settings from xapp1305: 

&gem0 {
    phy-handle = <&phy9>;
    phy9: phy@9 {
        reg = <0x9>;
        xlnx,phy-type = <0x4>;
    };
};

when I reverse DTB, gem0 is:

ethernet@ff0b0000 {
    compatible = "cdns,zynqmp-gem", "cdns,gem";
    status = "okay";
    interrupt-parent = <0x4>;
    interrupts = <0x0 0x39 0x4 0x0 0x39 0x4>;
    reg = <0x0 0xff0b0000 0x0 0x1000>;
    clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
    #address-cells = <0x1>;
    #size-cells = <0x0>;
    #stream-id-cells = <0x1>;
    iommus = <0x9 0x874>;
    power-domains = <0xe>;
    clocks = <0x3 0x1f 0x3 0x68 0x3 0x2d 0x3 0x31 0x3 0x2c>;
    phy-mode = "gmii";
    xlnx,ptp-enet-clock = <0x0>;
    local-mac-address = [00 0a 35 00 22 01];
    phy-handle = <0xf>;

    phy@9 {
        reg = <0x9>;
        xlnx,phy-type = <0x4>;
        linux,phandle = <0xf>;
        phandle = <0xf>;
    };
};

The external PHY is bootstrapped and seems to be configured correctly because we're able to get the LWIP baremetal application working on our custom board and don't have a MDIO bus connected to it.  

Currently I'm going down a new path and am starting with the 2018.3 sources of XAPP1305, adding our customized FSBL (configs our carrier board clk generator), changing the DTS machine name to template (so the ZCU102 board dtsi file isn't included), leaving the u-boot config as the zcu102 rev1.0 and crossing my fingers.  Oddly enough the first time I booted this configuration, eth0 was created but not on subsequent boots.  Am I wrong to think this approach would work?  I figured with this approach at least the kernel configuration and device tree should be correct.  Attached is the output of the console at bootup.  Eth0 shows up if the PCM/PCA driver is installed so I'm focusing on figuring out why it would only install sometimes:

[ 2.351567] macb ff0b0000.ethernet: Not enabling partial store and forward
[ 2.357350] libphy: MACB_mii_bus: probed
[ 2.362636] macb ff0b0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0b0000 irq 32 (00:0a:35:00:22:01)
[ 2.370667] Generic PHY ff0b0000.ethernet-ffffffff:09: attached PHY driver [Generic PHY] (mii_bus:phy_addr=ff0b0000.ethernet-ffffffff:09, irq=POLL)

And why I get this warning:

Configuring network interfaces... [ 5.419392] pps pps0: new PPS source ptp0
[ 5.423421] macb ff0b0000.ethernet: gem-ptp-timer ptp clock registered.
[ 5.430091] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc (v1.24.1) started
Sending discover...
[ 6.426374] macb ff0b0000.ethernet eth0: unable to generate target frequency: 125000000 Hz
[ 6.434643] macb ff0b0000.ethernet eth0: link up (1000/Full)
[ 6.440307] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
Sending discover...
Sending discover...
No lease, forking to background
done.

In the HW, we're currently setting the SGMII bridge inputs exactly like XAPP1305: phy address to 9, configuration vector to 0, configration_valid, an_adv_config_val and an_restart_config to 0, signal_detect to 1 and an_adv_config_vector to 55297.  I've only briefly looked at PG047 because the BM app was working so I figured it was connected correct... but maybe there's other requirements for Linux?

Thanks again for your help.

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Contributor
Contributor
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Registered: ‎05-09-2018

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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Also, do I have to put any init code for the SGMII bridge in the FSBL?  U-boot is able to get an IP address from the DHCP server and I can ping the host so I assume no and any configuration of GEM & SGMII bridge are taken care of by the kernel MACB device driver?

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Contributor
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Registered: ‎05-09-2018

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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The XAPP1305 bsp running on zcu102 behaves a little different at bootup; it detects the PHY as the PCS/PMA PHY, but my custom board calls it a generic PHY

 

on zcu102:

[ 1.680431] libphy: Fixed MDIO Bus: probed
[ 1.681441] tun: Universal TUN/TAP device driver, 1.6
[ 1.681564] CAN device driver interface
[ 1.682207] macb ff0b0000.ethernet: Not enabling partial store and forw
ard
[ 1.682663] libphy: MACB_mii_bus: probed
[ 1.756088] macb ff0b0000.ethernet eth0: Cadence GEM rev 0x50070106 at
0xff0b0000 irq 30 (00:0a:35:00:22:01)
[ 1.756112] Xilinx PCS/PMA PHY ff0b0000.ethernet-ffffffff:09: attached
PHY driver [Xilinx PCS/PMA PHY] (mii_bus:phy_addr=ff0b0000.ethernet-ffffff
ff:09, irq=POLL)

 

on custom board:

[ 2.338473] libphy: Fixed MDIO Bus: probed
[ 2.342298] tun: Universal TUN/TAP device driver, 1.6
[ 2.346472] CAN device driver interface
[ 2.351567] macb ff0b0000.ethernet: Not enabling partial store and forward
[ 2.357350] libphy: MACB_mii_bus: probed
[ 2.362636] macb ff0b0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0b0000 irq 32 (00:0a:35:00:22:01)
[ 2.370667] Generic PHY ff0b0000.ethernet-ffffffff:09: attached PHY driver [Generic PHY] (mii_bus:phy_addr=ff0b0000.ethernet-ffffffff:09, irq=POLL)

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-15-2011

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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@malburgj 

Please try to add phy-mode=sgmii in phy node.

 

    phy@9 {
        reg = <0x9>;

        phy-mode = "sgmii";
        xlnx,phy-type = <0x4>;
        linux,phandle = <0xf>;
        phandle = <0xf>;
    };

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Contributor
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Registered: ‎05-09-2018

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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That didn't seem to work. 

Doesn't it seem like udev isn't getting the event to install the Cadence & PHY modules?  On the zcu102 board I see eth0 has an interrupt (30) but on our board its missing.  And when I run /etc/init.d/udev start on zcu102 board, the Xilinx PCM/PCA PHY and Cadence GEM are getting added; not on our board.

Do I have to connect the AN interrupt (I didn't because its not connected in XAPP1305 and at least U-boot reads the MDIO registers for AN status)?

Does the XAPP1305 use a different kernel or have a kernel patch?  I'm asking because the 2018.1 version was called "... with external kernel"

The MDIO bus doesn't appear the the device tree but I've noticed some folks include mdio as a child to GEM and other threads say the MDIO bus is sometimes provided as a separate node.  I'm not adding it because it doesn't appear in the XAPP1305 DTS.

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Registered: ‎05-09-2018

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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results of uname -a for custom board using XAPP1305 BSP:

Linux ps_emio_eth_sgmii 4.14.0-xilinx-v2018.3 #1 SMP Sat May 18 16:42:13 UTC 2019 aarch64 GNU/Linux

results of uname -a for zcu102 board running XAPP1305 binary:

Linux ps_emio_eth_sgmii_with_external_kernel 4.14.0 #1 SMP Wed Jun 27 16:13:51 IST 2018 aarch64 GNU/Linux

... what does "with_external_kernel" mean?  kernel built outside of petalinux bsp?

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Registered: ‎05-09-2018

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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I'm digging through the MACB and phy device drivers and the mdio bus reads are returning all Fs.... still trying to figure out why.  Still not sure if this is a DT issue or issue w/ how we're bringing up the external PHY.

I know the node bindings exist in the Documentation directory of the kernel, but sinces the network branch can contain mdio, ethernet phy, along with different types of each, I don't find the documentation helpful.  Besides walking through the device drivers, is there another way to verify my device tree?.. just trying to eliminate variables. 

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Registered: ‎05-09-2018

回复: DTS for MAC/PHY for PCS/PMA/SGMII

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I probably had the GEM node correct for sometime.  Turns out the issue wasn't with the DT... kind of.  We have a AXI GPIO block in our design that takes the extenal clock generator (for the SGMII bridge) out of reset.  Although we were configuring the AXI GPIO block in the FSBL, Linux, at power-up, apparently writes to the AXI GPIO block to set the outputs to their default state; in our case, the default value (0x00) holds the SMII bridge in reset. :/

The is what I used for the GEM node; reading through the MACB driver, I understand that having a MDIO bus under the GEM is optional, so is the status property.  IMO reading through the driver was the best way to verify the DT node was correct.

&gem0 {
    phy-handle = <&phy9>;
    phy9: phy@9 {
        reg = <0x9>;
        xlnx,phy-type = <0x4>;
    };
};

To change the default value for Linux, I modified the AXI GPIO node with:

&axi_gpio_0 {
    xlnx,dout-default = <0x0002000F>;
    xlnx,dout-default-2 = <0x0>;
};

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