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Participant
Participant
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Registered: ‎11-09-2015

Desperaterly need help with AXI 16550a and RS-485

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Using the Zynq running Ubuntu linux on CPU0.  I have one stubborn RS-485 serial port that I can not get working.  There is data moving across the wire, but the other end is getting the data as corrput and kicking back an error code.  The UART is routed out to an LTC2865 Xcvr and the TX Enable is tied to a gpio. 

 

I am writing the GPIO high for TX Enable, sending the data.  Reading the LSR register until the transmitter empty bit is set and then dropping the tx enable.  This seems to work for the other 485 link I'm using, but it's at 19200 and the troubled link is at 9600.

 

Anyone help?

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Moderator
Moderator
14,698 Views
Registered: ‎07-31-2012

Hi,

 

Xilinx UART-lite IP core should have an output signal that can automatically drive the driver enable of an RS485 transceiver. There is currently no such feature in Xilinx IP for a UARTIP  that can support.

 

User can take a copy of uartlite ip RTLs/repo and try to modify uartlite_tx.vhd/.v to add a transmit enable output. 

This may help to communicate with RS485 transceiver.

 

Regards

Praveen

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Scholar
Scholar
8,841 Views
Registered: ‎02-27-2008

b,

 

Did you check all the other signals (CRS, RTS, CD, DTR, etc.)?  Sometimes terminal equipment or comm equip differ with those signals.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Moderator
Moderator
8,570 Views
Registered: ‎07-31-2012

Hi,

To summarize this issue, at 9600 baud rate they are encountering AXI Uart 16550 to RS485 tranceiver byte/data loss at tx side irrespective of controlling tx_enable signal via GPIO.

The idea of "polling the LSR until bit 4 is high (Tx Buffer Empty)" is good but I think should be on either bit 5 or bit 6 from Line Status Register(LSR) i.e. trasmitter hold register or transmitter empty  register. Could you please verify?

Apart from that, user should make use of a signal from UART to enable data on an external RS485 transceiver.

It looks like some specific signal is directly from the UART to external transceiver has been connected, but that signal de-asserts as soon as the TX FIFO is empty (i.e. before all tx bits are shifted out), making the last TX character disappear which is causing data loss/bad data received.

A possible approach could be to place some logic after the UART to dealy the de-assertion of the signal from UART to LT device for few cycles.  

 

Regards

Praveen


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Moderator
Moderator
14,699 Views
Registered: ‎07-31-2012

Hi,

 

Xilinx UART-lite IP core should have an output signal that can automatically drive the driver enable of an RS485 transceiver. There is currently no such feature in Xilinx IP for a UARTIP  that can support.

 

User can take a copy of uartlite ip RTLs/repo and try to modify uartlite_tx.vhd/.v to add a transmit enable output. 

This may help to communicate with RS485 transceiver.

 

Regards

Praveen

--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

--------------------------------------------------------------------------------------------


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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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Mentor
Mentor
8,536 Views
Registered: ‎06-10-2008

@pvenugo wrote:

Xilinx UART-lite IP core should have an output signal that can automatically drive the driver enable of an RS485 transceiver. There is currently no such feature in Xilinx IP for a UARTIP  that can support. 


I posted my modified UARTLITE recently here that accomplishes exactly that.