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Visitor kellyjp
Visitor
968 Views
Registered: ‎04-26-2018

Device Tree Generator: Regression in 2018.1 for Clocking Wizard IP

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Hi,

 

I have been using the Xilinx Device Tree Generator (DTG) to automatically generate the Linux device tree for my Zynq-7000 project using the relevant recipes in yocto meta-xilinx-tools.  I use the clocking wizard IP with AXI-Lite interface to allow dynamic reconfiguration from a linux device driver that uses the device tree to learn about how the clocking wizard IP is customised.

 

Prior to 2018.1 (2017.4 and earlier) the generated device tree for clocking wizard IP would be based on the actual customisation of the clocking wizard IP.  For example, if 4 clock outputs were enabled, the clock-output-names in the generated device tree would list 4 names and the names would be the same as those set when the IP was customised.  This behaviour made sense as the generated device tree matched the actual hardware and Linux device drivers could rely on the information in the device tree.

 

However, in 2018.1 the generated device tree for the clocking wizard IP now always generates 8 fixed clock-output-names.  The fixed generated names do not match the default customisation of the IP, the actual customisation of the IP, nor that of the MMCME2 or PLLE2 (which don't even have 8 clock outputs) primitives.

 

This regression seems to have been introduced in commit c9c6a7df548eaad6142f7ee9a1312d28872e2b7e.

 

Could this be fixed?

 

 

James

 

 

1 Solution

Accepted Solutions
Moderator
Moderator
1,212 Views
Registered: ‎09-12-2007

Re: Device Tree Generator: Regression in 2018.1 for Clocking Wizard IP

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Hi James,

 

Yes, I see this too. I created a simple zynq-7000 project with the clking wiz in the PL with the AXI interface enabled.

I created my DT using the HSI commands similar to below:

http://www.wiki.xilinx.com/ZCU102+Image+creation+in+OSL+flow

 

amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
clk_wiz_0: clk_wiz@43c00000 {
#clock-cells = <1>;
clock-names = "clk_in1", "s_axi_aclk";
clock-output-names = "clk_out0", "clk_out1", "clk_out2", "clk_out3", "clk_out4", "clk_out5", "clk_out6", "clk_out7";
clocks = <&clkc 15>, <&clkc 15>;
compatible = "xlnx,clocking-wizard";
reg = <0x43c00000 0x10000>;
speed-grade = <(-1)>;
};
};

 

You can see the changes in the driver here:

driver.PNG

 

I noticed you said that you are using a linux driver that will use the data in the clk_wiz node to determine the clocks used. So, I created a patch that will create a parameter with this information. I didnt want to overwrite the clock-output-names, as im assuming these are used elsewhere and may cause an issue. So, you would need to update your own driver to use he clock-output-names-old param instead.

 

the code in the patch is seen here:

patch.PNG

Note: this is just a copy and paste of the 2017.4 branch of the axi clk wiz driver from the DTG.

 

This will result in the updated DT here:

dt.PNG

Are you using Petalinux? If so, you can add the patch to the files folder in the recipe-bsp, and update the bbappend file to add this patch

 

 

3 Replies
Voyager
Voyager
926 Views
Registered: ‎06-20-2017

Re: Device Tree Generator: Regression in 2018.1 for Clocking Wizard IP

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I don't know the answer and I hope this answer doesn't delay an answer, but I have to say, wonderful post.  Very well researched and written.

Adaptable Processing coming to an IP address near you.
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Moderator
Moderator
1,213 Views
Registered: ‎09-12-2007

Re: Device Tree Generator: Regression in 2018.1 for Clocking Wizard IP

Jump to solution

Hi James,

 

Yes, I see this too. I created a simple zynq-7000 project with the clking wiz in the PL with the AXI interface enabled.

I created my DT using the HSI commands similar to below:

http://www.wiki.xilinx.com/ZCU102+Image+creation+in+OSL+flow

 

amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
clk_wiz_0: clk_wiz@43c00000 {
#clock-cells = <1>;
clock-names = "clk_in1", "s_axi_aclk";
clock-output-names = "clk_out0", "clk_out1", "clk_out2", "clk_out3", "clk_out4", "clk_out5", "clk_out6", "clk_out7";
clocks = <&clkc 15>, <&clkc 15>;
compatible = "xlnx,clocking-wizard";
reg = <0x43c00000 0x10000>;
speed-grade = <(-1)>;
};
};

 

You can see the changes in the driver here:

driver.PNG

 

I noticed you said that you are using a linux driver that will use the data in the clk_wiz node to determine the clocks used. So, I created a patch that will create a parameter with this information. I didnt want to overwrite the clock-output-names, as im assuming these are used elsewhere and may cause an issue. So, you would need to update your own driver to use he clock-output-names-old param instead.

 

the code in the patch is seen here:

patch.PNG

Note: this is just a copy and paste of the 2017.4 branch of the axi clk wiz driver from the DTG.

 

This will result in the updated DT here:

dt.PNG

Are you using Petalinux? If so, you can add the patch to the files folder in the recipe-bsp, and update the bbappend file to add this patch

 

 

Visitor kellyjp
Visitor
881 Views
Registered: ‎04-26-2018

Re: Device Tree Generator: Regression in 2018.1 for Clocking Wizard IP

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Stephen,

 

Thank you for the patch.  I don't use Petalinux - I use the Xilinx/yocto-manifests from Github.  However, I already have my own Yocto layer where I modify the device-tree recipe to add a board specific device tree fragment to the device_tree/data/kernel_dtsi/2018.1/BOARD directory of the device-tree-xlnx tree so it should be easy to modify that bbappend to add your patch to the tree as well.

 

Thanks again !

 

James

 

 

 

 

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