UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer tkato@poc.com
Observer
251 Views
Registered: ‎09-06-2019

Device tree overlay phandle error

Jump to solution

We have a system with 4 GEMs with a shared MDIO connected to GEM2. Since the drivers probe based on acesending memory (), the first two gems GEM0 and GEM1 are probed prior to having a phy handle and therefore never made available upon entering the kernel. 

 

To fix this we are trying to apply a device tree overlay in which enables 3 GEMs so that only GEM2 is initially probed. Here is the .dtsi:

 

/dts-v1/;
/plugin/;	/* allow undefined label references and record them */
/ {
	fragment@0 {
		target = <&gem0>;
		__overlay__ {
            		status = "okay";			
		};
	};
	fragment@1 {
		target = <&gem1>;
		__overlay__ {
            		status = "okay";			
		};
	};
	fragment@2 {
		target = <&gem3>;	
		__overlay__ {
            		status = "okay";			
		};
	};	
};

After following the commands presented in the wiki: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager

 

The following error are encountered:

# cd /configfs/device-tree/overlays/
# ls
# mkdir full
# echo -n "gem.dtbo" > full/path
[  309.784166] OF: resolver: no symbols in root of device tree.
[  309.789828] OF: resolver: overlay phandle fixup failed: -22
[  309.795393] create_overlay: Failed to create overlay (err=-22)

I'm unsure why the phandles are having issues with the device tree. Has anyone been able to resolve this?

0 Kudos
1 Solution

Accepted Solutions
Observer kawazome
Observer
135 Views
Registered: ‎04-02-2014

Re: Device tree overlay phandle error

Jump to solution

It seems that symbol information is not included in the root device tree.

When building the root device tree, add  -@  or --symbol to the dtc command.

For details, see “Compiling a Device Tree Overlay Blob (.dtbo) file from the pl.dts file.” at the following URL.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager

0 Kudos
6 Replies
Moderator
Moderator
206 Views
Registered: ‎09-12-2007

Re: Device tree overlay phandle error

Jump to solution

I have seen this before, but only for nodes in the pl.dtsi. Can you post your system-user.dtsi please?

0 Kudos
Observer tkato@poc.com
Observer
189 Views
Registered: ‎09-06-2019

Re: Device tree overlay phandle error

Jump to solution

Sure here it is:

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version: XSCT 2019.1
 * Today is: Wed Oct 30 22:54:19 2019
 */


/dts-v1/;
#include <dt-bindings/../../../../../board/zynqmp/dts/zynqmp.dtsi>
#include <dt-bindings/../../../../../board/zynqmp/dts/zynqmp-clk-ccf.dtsi>
#include <dt-bindings/../../../../../board/zynqmp/dts/pl.dtsi>
#include <dt-bindings/../../../../../board/zynqmp/dts/pcw.dtsi>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>

/ {
	chosen {
		bootargs = "earlycon clk_ignore_unused";
		stdout-path = "serial0:115200n8";
	};
	aliases {
		ethernet0 = &gem0;
		ethernet1 = &gem1;
		ethernet2 = &gem2;
		ethernet3 = &gem3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		serial0 = &uart0;
		serial1 = &uart1;
		spi0 = &qspi;
		spi1 = &spi0;
		spi2 = &spi1;
	};
	memory {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x7ff00000>;
	};
	
    /* supply voltage to audio codecs - grabbed from old DTS*/
	vcc_1v8: regulator-fixed-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "VCC_1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};
	vcc_3v3: regulaor-fixed-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VCC_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
		regulator-always-on; /* due vcc_1v8 leak to AIC34 VDDs */
	};
	
};

&gem3 {
	status = "disabled";
	phy-handle = <&phy1>;
	phy-mode = "rgmii";
	local-mac-address = [00 0a 35 00 00 03];
};

&gem2 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "rgmii";
	local-mac-address = [00 0a 35 00 00 02];
	phy0: phy@0 {
		reg = <0x0>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
		ti,rxctrl-strap-worka;
	};
	phy1: phy@1 {
		reg = <0x1>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
		ti,rxctrl-strap-worka;
	};
	phy8: phy@8 {
		reg = <0x8>;
        xlnx,phy-type = <0x4>;
	};
	phy2: phy@2 {
		reg = <0x2>;
        xlnx,phy-type = <0x4>;
	};
};

&gem1 {
	status = "disabled";
	phy-handle = <&phy8>;
	phy-mode = "sgmii";
	reset-gpios = <&gpio 45 0>;
	local-mac-address = [00 0a 35 00 00 01];
};

&gem0 {
	status = "disabled";
	phy-handle = <&phy2>;
	phy-mode = "sgmii";
	reset-gpios = <&gpio 13 0>;
	local-mac-address = [00 0a 35 00 00 00];
};


&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;

    
	acodec: tlv320aic34@18 {
		compatible = "ti,tlv320aic3x";
		reg = <0x18>;
		gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>; 
		AVDD-supply = <&vcc_3v3>;
		DRVDD-supply = <&vcc_3v3>;
		IOVDD-supply = <&vcc_1v8>;
		DVDD-supply = <&vcc_1v8>;
	};

	bcodec: tlv320aic34@19 {
		compatible = "ti,tlv320aic3x";
		reg = <0x19>;
		gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
		AVDD-supply = <&vcc_3v3>;
		DRVDD-supply = <&vcc_3v3>;
		IOVDD-supply = <&vcc_1v8>;
		DVDD-supply = <&vcc_1v8>;
	};
};

&spi0 {
	status = "okay";
	num-cs = <3>;
	is-decoded-cs = <0>;
	label = "Audio-SPI";
	spi0_0: spi5a@0 {
		compatible = "linux,spidev";
		reg = <0>;
		spi-max-frequency = <4000000>;
	};
	spi0_1: spi5a@1 {
		compatible = "linux,spidev";
		reg = <1>;
		spi-max-frequency = <4000000>;
	};
	spi0_2: spi5a@2 {
		compatible = "linux,spidev";
		reg = <2>;
		spi-max-frequency = <4000000>;
	};
};
0 Kudos
Observer kawazome
Observer
136 Views
Registered: ‎04-02-2014

Re: Device tree overlay phandle error

Jump to solution

It seems that symbol information is not included in the root device tree.

When building the root device tree, add  -@  or --symbol to the dtc command.

For details, see “Compiling a Device Tree Overlay Blob (.dtbo) file from the pl.dts file.” at the following URL.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager

0 Kudos
Observer tkato@poc.com
Observer
77 Views
Registered: ‎09-06-2019

Re: Device tree overlay phandle error

Jump to solution

Adding -@ seemed to do the trick but now the drivers don't actually seem to enable the additional GEMs. Are there further steps needed when attempting to enable a GEM once inside linux?

0 Kudos
Observer kawazome
Observer
40 Views
Registered: ‎04-02-2014

Re: Device tree overlay phandle error

Jump to solution

Device-tree-overlay can add and remove nodes, but unless you have a special case, changes in the properties in the node will not be reflected.

After booting Linux with the gem0, gem1, and gem3 nodes removed from the root device-tree, try adding the gem0, gem1, and gem3 nodes with the device-tree overlay.

0 Kudos
Observer tkato@poc.com
Observer
29 Views
Registered: ‎09-06-2019

Re: Device tree overlay phandle error

Jump to solution

After fixing the overlay errors and adding in some TI phy attributes we were able to properly link the MACB drivers with the PHYs. 

 

I'll also give your suggested method a try as well. 

 

Thanks!

0 Kudos