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Observer
Observer
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Registered: ‎05-04-2015

Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi,

 

We have a custom board with a Zynq-100 using two Marvell 88e1512 PHYs for dual ethernet and have not been able to get eth1 up and running on xilinx-linux(eth0 works fine). To summarize the problem, it appears that the mdio/phy/enet driver doesn't recognize the second PHY at address 1. I have verified that I can read the OUI bits from the PHY registers using u-boot (mdio read 0 2, mdio read 1 2 - other addresses do not respond).

 

The Marvell PHYs have a single bit of PHY address configuration, the CONFIG pin, we have PHY0 CONFIG pin pulled down, and PHY1 CONFIG pin pulled high. We swapped the PHY CONFIG pins (essentially swapping PHY0 and PHY1) and found that the erstwhile PHY1 would be detected, configured and would detect link status, but we couldn't transfer data because the data lines are hardwired to the enet1 PS on the Zynq (note that the MDIO bus is connected to both PHYs).

 

I have investigated previous threads on this issue and it appears that dual PHY support on a single MDIO bus was fixed in 2014.4. I even checked the xilinx_emacps.c patch in one of these threads to make sure we had it.

 

Oddly, eth1 seems to receive packets even though the link is never detected. It's almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn't been configured. i.e. the MDIO interface doesn't work, but the RGMII interface does. (see output below)

 

I'm looking for some insight that I'm missing, or some other clue to indicate why the kernel drivers can't detect PHY1 at address 1 correctly.

 

FYI, Tool and Software tags:

======================

dtc: v1.4.1
xilinx device tree: xilinx-v2015.4
u-boot: xilinx-v2015.4-3852-g8859a54
kernel: xilinx-v2015.2.03
Xilinx SDK & Tools: 2015.2

 

I have looked at the following link, and it appears that the issue of supporting two PHYs was solved in 2014.4, and we are using 2015.2 and above.

https://forums.xilinx.com/t5/Embedded-Linux/zynq-linux-dual-emacps-gem-problem/td-p/263964

 

When booting Linux I get the following messages:

...
libphy: MACB_mii_bus: probed
mdio_bus e000b000.etherne: /amba/ethernet@e000b000/mdio has invalid PHY address
mdio_bus e000b000.etherne: scan phy mdio at address 0
mdio_bus e000b000.etherne: scan phy mdio at address 1
mdio_bus e000b000.etherne: scan phy mdio at address 2
mdio_bus e000b000.etherne: scan phy mdio at address 3
mdio_bus e000b000.etherne: scan phy mdio at address 4
mdio_bus e000b000.etherne: scan phy mdio at address 5
mdio_bus e000b000.etherne: scan phy mdio at address 6
mdio_bus e000b000.etherne: scan phy mdio at address 7
mdio_bus e000b000.etherne: scan phy mdio at address 8
mdio_bus e000b000.etherne: scan phy mdio at address 9
mdio_bus e000b000.etherne: scan phy mdio at address 10
mdio_bus e000b000.etherne: scan phy mdio at address 11
mdio_bus e000b000.etherne: scan phy mdio at address 12
mdio_bus e000b000.etherne: scan phy mdio at address 13
mdio_bus e000b000.etherne: scan phy mdio at address 14
mdio_bus e000b000.etherne: scan phy mdio at address 15
mdio_bus e000b000.etherne: scan phy mdio at address 16
mdio_bus e000b000.etherne: scan phy mdio at address 17
mdio_bus e000b000.etherne: scan phy mdio at address 18
mdio_bus e000b000.etherne: scan phy mdio at address 19
mdio_bus e000b000.etherne: scan phy mdio at address 20
mdio_bus e000b000.etherne: scan phy mdio at address 21
mdio_bus e000b000.etherne: scan phy mdio at address 22
mdio_bus e000b000.etherne: scan phy mdio at address 23
mdio_bus e000b000.etherne: scan phy mdio at address 24
mdio_bus e000b000.etherne: scan phy mdio at address 25
mdio_bus e000b000.etherne: scan phy mdio at address 26
mdio_bus e000b000.etherne: scan phy mdio at address 27
mdio_bus e000b000.etherne: scan phy mdio at address 28
mdio_bus e000b000.etherne: scan phy mdio at address 29
mdio_bus e000b000.etherne: scan phy mdio at address 30
mdio_bus e000b000.etherne: scan phy mdio at address 31
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 147 (00:0a:35:00:01:22)
macb e000b000.ethernet eth0: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000b000.etherne:00, irq=-1)
libphy: MACB_mii_bus: probed
macb e000c000.ethernet eth1: Cadence GEM rev 0x00020118 at 0xe000c000 irq 148 (00:0a:35:00:00:01)
macb e000c000.ethernet eth1: attached PHY driver [Generic PHY] (mii_bus:phy_addr=e000c000.etherne:00, irq=-1)
...

 

Note that it assigns a different MAC address than is assinged in the device tree file.
Note that it attaches a Generic PHY driver to eth1, and the phy id is :00 instead of :01 as specified in the device tree file

 

Device Tree File:

=============

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version: HSI 2015.2
 * Today is: Thu Feb 18 10:21:36 2016
*/


/dts-v1/;
/include/ "zynq-7000.dtsi"
/include/ "pl.dtsi"
/ {
	cpus {
		cpu@0 {
			operating-points = <666666 1000000 333333 1000000>;
		};
	};
	chosen {
		bootargs = "console=ttyPS0,115200";
		stdout-path = "serial0:115200n8";
	};
	aliases {
		ethernet0 = &gem0;
		ethernet1 = &gem1;
		serial0 = &uart0;
		serial1 = &uart1;
		spi0 = &qspi;
	};
	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};
};
&gem0 {
	local-mac-address = [00 0a 35 00 00 00];
	phy-mode = "rgmii-id";
	status = "okay";
	xlnx,ptp-enet-clock = <0x69f6bcb>;
	phy-handle = <&ethernet_phy0>;
        #address-cells = <1>;
     	#size-cells = <0>;
	mdio {
	        #address-cells = <1>;
	     	#size-cells = <0>;
	     	ethernet_phy0: ethernet-phy@0 {
			compatible = "marvell,88e1510";
			device_type = "ethernet-phy";
	                reg = <0>;
		};
		ethernet_phy1: ethernet-phy@1 {
			compatible = "marvell,88e1510";
			device_type = "ethernet-phy";
			reg = <1>;
		};
	};
};
&gem1 {
	local-mac-address = [00 0a 35 00 00 01];
	phy-mode = "rgmii-id";
	status = "okay";
	xlnx,ptp-enet-clock = <0x69f6bcb>;
	phy-handle = <&ethernet_phy1>;
        #address-cells = <1>;
     	#size-cells = <0>;
};
&gpio0 {
	emio-gpio-width = <60>;
	gpio-mask-high = <0x0>;
	gpio-mask-low = <0x5600>;
};
&i2c0 {
	clock-frequency = <400000>;
	status = "okay";
};
&intc {
	num_cpus = <2>;
	num_interrupts = <96>;
};
&qspi {
	is-dual = <0>;
	num-cs = <1>;
	status = "okay";
};
&sdhci0 {
	status = "okay";
	xlnx,has-cd = <0x0>;
	xlnx,has-power = <0x0>;
	xlnx,has-wp = <0x0>;
	broken-cd;
	wp-inverted;
};
&uart0 {
	current-speed = <115200>;
	device_type = "serial";
	port-number = <0>;
	status = "okay";
};
&uart1 {
	current-speed = <115200>;
	device_type = "serial";
	port-number = <1>;
	status = "okay";
};
&clkc {
	fclk-enable = <0x3>;
	ps-clk-frequency = <33333333>;
};

 

 

I tried switching eth0 to PHY1 and eth1 to PHY0, but the kernel seems to prevent and switch this attempt.

 

Evidence that the RGMII interface is functioning even though we are not talking over the MDIO interface:

root@localhost:~# ifconfig eth0 up 192.168.1.12

root@localhost:~# ifconfig eth1 up 192.168.66.12
root@localhost:~# ifconfig
eth0      Link encap:Ethernet  HWaddr 00:0a:35:00:01:22  
          inet addr:192.168.1.12  Bcast:192.168.1.255  Mask:255.255.255.0
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:91 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:7348 (7.3 KB)  TX bytes:0 (0.0 B)
          Interrupt:147 Base address:0xb000

eth1      Link encap:Ethernet  HWaddr 00:0a:35:00:00:01  
          inet addr:192.168.66.12  Bcast:192.168.66.255  Mask:255.255.255.0
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:3 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:138 (138.0 B)  TX bytes:0 (0.0 B)
          Interrupt:148 Base address:0xc000

(Note that I am using two different sub-nets - the 192.168.66 subnet is connected to our host computer over a switch and no other traffic than the pings I send is seen)

 

Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related. Reluctant to pursue it as we are not using Petalinux:

https://forums.xilinx.com/t5/Embedded-Linux/Multiple-ethernet-port-problem/td-p/656153

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Observer
Observer
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Registered: ‎05-04-2015

Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Verified fix for this problem.

 

Patch files attached. Patch is applicable ONLY to the 2016.1 kernel.

 

Do as follows:

 

1. checkout, patch, and build 2016.1 kernel

 

$ git clone --branch xilinx-v2016.1 --depth 1 https://github.com/Xilinx/linux-xlnx.git
$ cd linux-xlnx
$ git apply 0001-net-macb-Add-MDIO-driver-for-accessing-multiple-PHY-.patch
$ git apply 0002-Documentation-devictree-Add-macb-mdio-bindings.patch
$ make ARCH=arm xilinx_zynq_defconfig
$ make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage

 

 

2. modify your device tree file as follows:

 

2a. Add mdio in the top level:

 

/ {
    cpus {
        cpu@0 {
            operating-points = <666666 1000000 333333 1000000>;
        };
    };
    chosen {
        bootargs = "console=ttyPS0,115200";
        stdout-path = "serial0:115200n8";
    };
    aliases {
        ethernet0 = &gem0;
        ethernet1 = &gem1;
        serial0 = &uart0;
        serial1 = &uart1;
        spi0 = &qspi;
    };
    memory {
        device_type = "memory";
        reg = <0x0 0x40000000>;
    };
    mdio {
         compatible = "cdns,macb-mdio";
         reg = <0xe000b000 0x1000>;
         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
         clock-names = "pclk", "hclk", "tx_clk";
         #address-cells = <1>;
         #size-cells = <0>;
         phy0: phy@0 {
              compatible = "marvell";
              device_type = "ethernet-phy";
              reg = <0>;
        } ;
            phy1: phy@1 {
                 compatible = "marvell";
                 device_type = "ethernet-phy";
                 reg = <1>;
              } ;
       };
};

 

2b. Add the phy handle to the gem sections:

 

&gem0 {
    local-mac-address = [00 0a 35 00 00 00];
    phy-mode = "rgmii-id";
    status = "okay";
    xlnx,ptp-enet-clock = <0x69f6bcb>;
    phy-handle = <&phy0>;
};
&gem1 {
    local-mac-address = [00 0a 35 00 00 01];
    phy-mode = "rgmii-id";
    status = "okay";
    xlnx,ptp-enet-clock = <0x69f6bcb>;
    phy-handle = <&phy1>;
};

 

3. Build the device tree blob, and copy uImage and the .dtb file to your boot partition.

 

Hope this helps everyone with this problem...

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Professor
Professor
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Registered: ‎08-14-2007

Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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The 88E1512 CONFIG pin impements a 2-bit function where one bit is PHY address bit 0 and the other is the interface voltage.  If you tie the pin low, you get PHY address 0 = 0 and the interface voltage at 3.3V.  If you tie the pin high, you get PHY address 0 = 1 and interface voltage 2.5V.  I assume you use the same interface voltage for both PHY chips.  If they both operate at 3.3V, then one PHY should have CONFIG tied to Vss (PHY ADDR 0) and the other to LED[0] (PHY ADDR 1).  If they both operate at 2.5V when one should be tied to Vcc (PHY ADDR 1) and the other tied to LED[1] (PHY ADDR 0).

-- Gabor
CONFIG_mapping.PNG
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Observer
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Thanks for the quick response Gabor,

 

I had seen that, but we run both PHYs a 1.8v (similar to the MicroZed, although it has only a single PHY). I don't have the Marvell datasheet handy, but recall seeing that when run a 1.8v that the LED bits are ignored, but perhaps that was for a differet PHY.

 

There is no CONFIG setting for 1.8v, yet our PHY0 works correctly. This also doesn't explain how I can read the OUI bits from register 2 on both PHY1 and PHY0 using u-boot. I suspect this is a software issue.

 

Thanks,

Charlie

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Explorer
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Registered: ‎02-22-2012

Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Have you tried with slightly rearranged device tree like this?

 


&gem0 { local-mac-address = [00 0a 35 00 00 00]; phy-mode = "rgmii-id"; status = "okay"; xlnx,ptp-enet-clock = <0x69f6bcb>; phy-handle = <&ethernet_phy0>; #address-cells = <1>; #size-cells = <0>;
ethernet_phy0: ethernet-phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; &gem1 { local-mac-address = [00 0a 35 00 00 01]; phy-mode = "rgmii-id"; status = "okay"; xlnx,ptp-enet-clock = <0x69f6bcb>; phy-handle = <&ethernet_phy1>; #address-cells = <1>; #size-cells = <0>;

ethernet_phy1: ethernet-phy@1 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <1>; }; };

 

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Observer
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi Primoz,

 

Thanks for the reply. Yes, I have tried it, but eth1 still doesn't work.

 

According to:

https://forums.xilinx.com/t5/Embedded-Linux/zynq-linux-dual-emacps-gem-problem/td-p/263964/page/3

if you are using two PHYs on the same MDIO, you need to group them under the MDIO block, or you will get an error. However, I don't see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1:

 

libphy: MACB_mii_bus: probed
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 147 (00:0a:35:00:01:22)
macb e000b000.ethernet eth0: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000b000.etherne:00, irq=-1)
libphy: MACB_mii_bus: probed
macb e000c000.ethernet eth1: Cadence GEM rev 0x00020118 at 0xe000c000 irq 148 (00:0a:35:00:00:01)
macb e000c000.ethernet eth1: attached PHY driver [Generic PHY] (mii_bus:phy_addr=e000c000.etherne:01, irq=-1)
e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

However, eth1 still doesn't work correctly. I enable eth0 and see transactions on the MDIO bus. I disable eth0 and enable eth1 and see NO transactions on the MDIO bus. Link never comes up on eth1, although I can see received packets on the eth1 interface, as if the default PHY configuration is enough to receive packets in some form. Again, this appears to be a software issue. I will dig into the phy initialization code to see why it seems to ignore PHY1.

 

I verified with u-boot that I can talk to both PHYs over the MDIO bus, using the correct PHY addresses of 0 and 1.

 

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Adventurer
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Try to

set PHY0 -> address 1

set PHY1 -> address 2

 

Address 0 might be / is an MDIO broadcast address (correct me if I'm wrong please).

 

With Regards

TJ

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Observer
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi TJ,

 

Thanks for the advice. I have tried that previously (and once againt to verify). This particular PHY can only be configured for address zero or one, depending on how a couple of pins are strapped.

 

I've verified that both PHYs respond when using the u-boot mdio commands, however, when running the Linux kernel code, it appears to ignore or not see the addresses in the device tree, and it also seems to not identify PHY1 correctly, attaching a "Generic PHY" driver to it.

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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@charleeh

 

What other kernel settings did you have to enable to allow the Marvell 88e1512 PHY to have the correct drivers from petalinux? We are running a single Marvell 88e1512 on a custom board, and it refuses to work at all. I've tried your device tree example as well as different examples found:

http://www.xilinx.com/support/answers/65504.html

http://zedboard.org/content/marvell-88e1518-phy-driver

http://www.xilinx.com/support/answers/59554.html

 

petalinux-config -c kernel doesn't seem to provide support for our exact version of Marvell PHY, but rather ive enabled the following settings:

Device Drivers->
     [*]Network device support ->
          [*]Ethernet driver support ->
               [*] Marvell devices
          [*] PHY Device support and infastructure -->
               [*] Drivers for Marvell PHYs

 

Thanks.

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Observer
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi,

 

Check the reset pin to the PHYs. The software doesn't seem to do anything with it. We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot.

 

Did you try running ping with u-boot? We verified that before trying it in the kernel.

 

We aren't using petalinux, but the kernel config stuff all looks the same.

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Thanks for the tips,

 

Ping does not work in U-boot, so i am now investigating into the reset. Thanks again.

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Scholar
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi,

 

maybe I can enlight a bit:

 

dual PS MIO 88E1512 is working as of HARDWARE interface with no issues, this is the reason you see it working in uboot. Uboot just uses the PHY addresses 0 and 1, adresses the correct PHY's and everything seems OK.

 

http://www.xilinx.com/support/answers/59554.html

 

This AR says: "should use" non-zero PHY address, what means that 88E1512 is not recommended.

 

With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 (valid address) remains not configured and is fully not accessible.

 

To my understanding this is a MAJOR bug in linux :( do not know how to fight with this issue.

I think in some earlier petalinux versions dual PS MIO 0,1 PHY setup was working, with 2015.4 it is sure not working (not working any more).

 

unless there is some trick?

 

 

 

 

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Observer
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi,

 

Thanks for the information. This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren't zero. I will dig into the kernel code to see if there is a workaround.

 

Charlie

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Scholar
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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please let us know if you find something.

 

thank you in advance

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Professor
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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I haven't used Zynq before, so maybe this suggestion is not appropriate.  However if the MDIO lines route through the fabric, you could add some logic to flip an address bit between the controller and the PHY MDIO pin.  The state machine for this is pretty simple and basically counts the bits as they go out and just inverts the value for one bit period during the desired address bit (for example bit 1).  Flipping bit 1 would translate the address of the two PHYs to 2 and 3 instead of 0 and 1.  It's likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software.

-- Gabor
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Scholar
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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thats a good advice but

 

1) if you have ETH on PS MIO, then you can not route MDIO to EMIO, this is not supported

2) if you have PCB ready, you could not use this trick either as the wiring would be fixed

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi Charleeh,

 

Have you solved the issue with 88E1512 PHY_addr being 0 and 1 on the same MDIO bus? I Have met the same problem, hope could get some ideas from you! Thanks a lot! 

 

 

 

Best Regards,

Lydia

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Observer
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi Lydia,

 

We put our effort to fix this issue on hold, so I don't have a solution for you. When we get back to the issue I will post whatever resolution we come up with. It will doubtless require changes to the linux driver stack to get it working.

 

Charlie

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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hello!i find i have the same question as you meet. i also use 88E1518 and connect it to MIO and manage the same MDC and MDIO. Do you have any further information about this question?

i am stucked at this for few days and without any method.

 

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Visitor
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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sorry. i mean the 88E1512, not 88E1518.
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Observer
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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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According to a Xilinx FAE:

 

"The latest kernel will be using the MACB drivers. However we have a patch that will include the support to enable Dual Ethernet configuration in MACB driver. This has been tested on Zynq Ultrascale with a Daughter card. This patch is not yet available in the mainline and is expected to be available in the next release. So I would suggest you to try testing the setup in 2016.3 once it is available and test this interface."

 

In other words, the newest kernel(s) are using the MACB drivers, not the Xilinx emac drivers.There was a fix in the emac drivers, but it's not being used anymore. The device tree in the newer kernels uses the MACB drivers.

 

FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases:

https://lkml.org/lkml/2016/5/13/167

 

Also, the 2016.3 release is supposed to be out yesterday ;) (10/11/2016). FAE reports it will be out 10/13/2016.

 

Hope this helps. I will post when I get the new release and test it.

 

Charlie

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Did you have a chance to solve shared mdio problem in 2016.3? I cant try it due to my situation, if you try it can you please give information about 2016.3 shared mdio problem?

 

 

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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There was a little communication confusion with Xilinx. It will be fixed in the 2016.3 version of Petalinux, not out until 10/30/2016.

 

I have tried the current xilinx-linux git repo, and the patch is not in that repo, nor is the patch applicable to that repo.

 

Hoping to get a pre-release of the 2016.3 Petalinux for verification.

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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thats a good advice but 1) if you have ETH on PS MIO, then you can not route MDIO to EMIO, this is not supported 2) if you have PCB ready, you could not use this trick either as the wiring would be fixed

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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So 2016.3 is out now. I tried it without success. Anyone else had it work?

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi,

 

Xilinx was a little confused. It's not being released in the petalinux 2016.3 release after all.

 

I have gotten a patch that looks like it applies to the 2016.1 release, and am trying that. I'll update you when I have more information.

 

Charlie

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Verified fix for this problem.

 

Patch files attached. Patch is applicable ONLY to the 2016.1 kernel.

 

Do as follows:

 

1. checkout, patch, and build 2016.1 kernel

 

$ git clone --branch xilinx-v2016.1 --depth 1 https://github.com/Xilinx/linux-xlnx.git
$ cd linux-xlnx
$ git apply 0001-net-macb-Add-MDIO-driver-for-accessing-multiple-PHY-.patch
$ git apply 0002-Documentation-devictree-Add-macb-mdio-bindings.patch
$ make ARCH=arm xilinx_zynq_defconfig
$ make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage

 

 

2. modify your device tree file as follows:

 

2a. Add mdio in the top level:

 

/ {
    cpus {
        cpu@0 {
            operating-points = <666666 1000000 333333 1000000>;
        };
    };
    chosen {
        bootargs = "console=ttyPS0,115200";
        stdout-path = "serial0:115200n8";
    };
    aliases {
        ethernet0 = &gem0;
        ethernet1 = &gem1;
        serial0 = &uart0;
        serial1 = &uart1;
        spi0 = &qspi;
    };
    memory {
        device_type = "memory";
        reg = <0x0 0x40000000>;
    };
    mdio {
         compatible = "cdns,macb-mdio";
         reg = <0xe000b000 0x1000>;
         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
         clock-names = "pclk", "hclk", "tx_clk";
         #address-cells = <1>;
         #size-cells = <0>;
         phy0: phy@0 {
              compatible = "marvell";
              device_type = "ethernet-phy";
              reg = <0>;
        } ;
            phy1: phy@1 {
                 compatible = "marvell";
                 device_type = "ethernet-phy";
                 reg = <1>;
              } ;
       };
};

 

2b. Add the phy handle to the gem sections:

 

&gem0 {
    local-mac-address = [00 0a 35 00 00 00];
    phy-mode = "rgmii-id";
    status = "okay";
    xlnx,ptp-enet-clock = <0x69f6bcb>;
    phy-handle = <&phy0>;
};
&gem1 {
    local-mac-address = [00 0a 35 00 00 01];
    phy-mode = "rgmii-id";
    status = "okay";
    xlnx,ptp-enet-clock = <0x69f6bcb>;
    phy-handle = <&phy1>;
};

 

3. Build the device tree blob, and copy uImage and the .dtb file to your boot partition.

 

Hope this helps everyone with this problem...

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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hi,

 

this is the official patch. https://www.xilinx.com/support/answers/69132.html

 

--hs

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hi,

 

Currently we have a custom Zynq Utrascale+ ZU9EG design with two GEM (1 & 3) using two RGMII connecting two independent TI DP83867 (same as ZCU102), see attached PDF.

 

These two PHYs are at address 0x0 and 0x1 and share a single MDIO (as described in the post)

 

In single GEM configuration, Petalinux BSP works straight forward on both GEM1 or GEM3. We are not able to run our dual GEM config.

 

We have tried to apply the patch, but does'nt works ... we are facing petalinux.build errors 

This patch does't explain how to implement it.

 

Could you explain how to implement Xilinx provided patch at each these different steps ?

 

  1. Vivado 
  2. device tree (system_user.dtsi ?)
  3. Linux Kernel

Thanks

Panou

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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Hello,

 

Does the patch post of 2016.1 resolves the dual mac issue ?

Should it be used with the device tree posted in your initial question above or is it sufficient to use the device tree parts as described in the post with the patch (the accepted answer)  ?

 

 

I also see that fixed phy/fixed link is not used. Isn't it required ?

 

Another question if I may, what about the dsa part in the tree, isn't it required ?

 

 

Thank you,

Ran

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Re: Dual Marvell 88e1512 PHY Ethernet problem - Xilinx LInux

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The issue was with the PHY not the MAC, which is implemented in the Zynq PS.

 

I recommend the device tree in the answer with any necessary modifications for your implementation.

 

Not sure about the dsa or link. Haven't worked on this in a couple of years.

 

Best of luck.

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