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James_Edgar
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Registered: ‎08-24-2020

EMIO not toggling in PL after JTAG bitstream update

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I have ported a Vivado project that worked on the ZCU111 board to the ZCU208 board.  After bringing up the ZCU208 board with the demo linux image, I download my new PL image over JTAG.

When I toggle the emio gpios using:

echo 1 > /sys/class/gpio/gpio458/value

the value changes from 0 to 1 in Linux.  However, when monitoring the output in an ILA in Vivado, the output on emio_gpio_o does not change from 0 to 1.

These emio pins were not used in the original design, but they are available in:

/sys/class/gpio/

and I am able to enable them as outputs.  I can modify the project to use a different control strategy (ie AXI peripheral) but I would like to understand why I am not able to control these internal PS to PL signals.  I did see references to the PS-PL level shifters.  I am not sure how to confirm this is enabled.  Trying to read REQ_PWRUP_INT_EN at 0XFFD80118 generates a bus error.  Is there a way to confirm this is enabled from Linux user space?

Any other suggestions on other things to check would be appreciated.  I was not able to use the fpgautil alternative for loading the new bitfile, which is how I had been loading it for the previous board.  It appears the Linux image does not have the proper settings for allocating memory to download the image this way.  Perhaps additional steps are required when the image is downloaded over jtag?

Thanks,

James

 

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James_Edgar
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Registered: ‎08-24-2020

Apparently, the EMIO mapping was different that I had expected.  There were 18 AXI gpio used in the original project.  Although the output of the Zynq processor generates [94:0] emio outputs, the higher outputs [94:18] appear to be mapped to the gpios in bank gpiochip320.  There are three separate banks gpiochip494, gpiochip496, and gpiochip504 which seem to take over the lower emios [17:0].

James

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James_Edgar
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Registered: ‎08-24-2020

Apparently, the EMIO mapping was different that I had expected.  There were 18 AXI gpio used in the original project.  Although the output of the Zynq processor generates [94:0] emio outputs, the higher outputs [94:18] appear to be mapped to the gpios in bank gpiochip320.  There are three separate banks gpiochip494, gpiochip496, and gpiochip504 which seem to take over the lower emios [17:0].

James

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