01-24-2018 08:35 AM
I'm porting a Zynq-7000 design to Zynq MPSoC (ZCU102) and can't get the PL clocks working. My design uses PL0, 1, and 2 running at 100, 200, and 200MHz respectively. All three clocks are enabled in the ZynqMP Processor System IP block with the respectively frequencies. When I boot into Linux and try to read registers from IP on the PL2 clock domain, I get a Bus Error. Chipscope cores running off this clock also don't respond. I am able to access the registers and Chipscope when the logic is moved to the PL0 domain.
I decompiled the devicetree from Petalinux and found these nodes:
status = "disabled";
compatible = "xlnx,fclk";
clocks = <0x3 0x48>;
I overrode the status property to "okay" in system-user.dtsi and the logic now responds. I can't verify that the frequency is correct, though. Linux reports from /sys/kernel/debug/clk/pl0/clk_rate 9375000 vs the expected 200000000 (or close).
Is there documentation anywhere for properly configuring the PL clocks in Linux? As far as I can tell the configuration is correct in Vivado and the HDF/FSBL file.
01-25-2018 07:14 AM
Open a block diagram of the design,
Double click on the PS block. Clock configuration selection is over on the left, click it. It will take to the configuration screen. Note the frequency chosen was't exact. 199.975 MHz vs. 200 (choice of actual crystal used on zcu102 board).
01-25-2018 11:52 AM
I already had these configured in Vivado. This is an issue with Linux. I dug into the Petalinux devicetree and found the fclk0,1,2, and 3 nodes had ' status = "disabled"; '. The clocks are on when I build with ' status = "okay"; ' The compatible driver is set to "xlnx,fclk", which doesn't seem to set the frequency at all, so I'm hopeful that it keeps the frequency as initially programmed in the FSBL.
Is there a procedure for handling these clocks in Petalinux for MPSoC? I've found documentation on Zynq-7000 FCLK but not much for MPSoC.
02-07-2018 11:30 PM
Hello, we have the same problem as you. we use xczu3eg-sfva625-1L-i soc chip, and vivado 2017.2 tool.
In our design, we creat a new ip with 8 registers. The value of each register is fixed. Then we read the registers, and find that, only address 00h and 10h can be read correctly, other addresses return 0 value when we read. Then we want to see what happened, but the chipscope can not work. So, we route the pl_clk0(PS0) to an LED on the board, and measure it with the oscillscope, and the frequency is 1 MHz, not matched the valued we have configured 100 Mhz.
Our design is very simple, consisting of a SoC Core, a reset module, a AXI Interconnect bridge, and a new created ip with some registers.
Have you solved your problem ?
If yes, can you tell me the method ?
02-08-2018 02:48 PM
Do you see this frequency problem when running baremetal or Linux?
I would first try to 'debug' a baremetal app using SDK. This way, psu_init will be used by SDK to initialize the pl clk freq. Or, if running Linux, stop in uboot to verify the freq.
Something to be careful of is 2017.2 had an issue where the vivado exported .hdf would not properly be extracted into an SDK workspace. Search for ARs related to 2017.2 and .hdf. I believe there is an available patch for both sdk and petalinux.
Regarding chipscope, have you tried adding the System ILA to your IPI project? It makes it very easy to connect to AXI or other types of ports.
For a simple register interface, the fact that two of multiple registers are working, I question if there is an error in the register IP. System ILA should help to shed some light.
02-08-2018 06:31 PM
06-13-2018 02:14 AM
I had a similar problem. The pl clocks worked when running bare-metal code throught the SDK, but not with petalinux. The problem was that I had my power manager turned off (I deliberately disabled it in kernel config) and aparently the power manager controls these clocks.