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Visitor santonop
Visitor
5,098 Views
Registered: ‎02-20-2012

Error compiling kernel virtex 5

Hello from Greece, 

 

I try to compile the linux kernel for the virtex-5 family. I followed the instructions from xilinx.wikidot.com.

I used the v1.0. compiler tools but I got many errors during the compiler process and now I use v2.0.

I constantly get this error during the compiling process:

make[1]:*** No rule to make target 'arch/microblaze/boot/xilinx.dtb', needed bt 'arch/microblaze/boot/system.dtb'. Stop.

make: *** [arch/microblaze/boot] Error 2

 

I thought that the error has to do with this from the wiki:

No DTS In Raw Linux
When using the "linux.bin" to load the kernel, it seems that the DTS file is not compiled to DTB. When "linux.bin" is linked, the DTB is missing and when executing the kernel it seems to hang (no output). To check if this might be an issue for you, check the "arch/microblaze/boot" directory for a file with "dtb" extension. If you see your "linux.bin" but no "dtb" file, it is likely the build is incomplete.

To solve, first build the simple image (which depend on the dtb and as such will generate it) and then the raw linux binary like this:

make clean
make simpleImage.xilinx linux.bin

 So I typed:

make ARCH=microblaze simpleImage

 

 and then the given command. But I had the same error.

 

If you need anything from my files (e.g.  .dts ) just write it down. The microblaze version is 8.00.b and I try to compile the big endian architecture.

thank you in advance...

Stavros


 

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3 Replies
Visitor santonop
Visitor
5,075 Views
Registered: ‎02-20-2012

Re: Error compiling kernel virtex 5

Well the error surely has to do, with my .dts file.

I tried to complile the kernel with the dts file fro the reference design and there was no problem.

I tried to compare the two files in order to find the error. The difference is at the bootargs in the chosen section.

My .dts file is:

/*
 * Device Tree Generator version: 1.3
 *
 * (C) Copyright 2007-2008 Xilinx, Inc.
 * (C) Copyright 2007-2009 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * CAUTION: This file is automatically generated by libgen.
 * Version: Xilinx EDK 12.4 EDK_MS4.81d
 *
 * XPS project directory: testlinux_2
 */

/dts-v1/;
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "xlnx,microblaze";
	model = "testing";
	DDR2_SDRAM: memory@50000000 {
		device_type = "memory";
		reg = < 0x50000000 0x10000000 >;
	} ;
	aliases {
		ethernet0 = &Hard_Ethernet_MAC;
		serial0 = &RS232_Uart_1;
	} ;
	chosen {
		bootargs = "console=tty0 root=/dev/ram";
		linux,stdout-path = "/plb@0/tft@a0000000";
	} ;
	cpus {
		#address-cells = <1>;
		#cpus = <0x1>;
		#size-cells = <0>;
		microblaze_0: cpu@0 {
			clock-frequency = <100000000>;
			compatible = "xlnx,microblaze-8.00.b";
			d-cache-baseaddr = <0x50000000>;
			d-cache-highaddr = <0x5fffffff>;
			d-cache-line-size = <0x10>;
			d-cache-size = <0x800>;
			device_type = "cpu";
			i-cache-baseaddr = <0x50000000>;
			i-cache-highaddr = <0x5fffffff>;
			i-cache-line-size = <0x10>;
			i-cache-size = <0x800>;
			model = "microblaze,8.00.b";
			reg = <0>;
			timebase-frequency = <100000000>;
			xlnx,addr-tag-bits = <0x11>;
			xlnx,allow-dcache-wr = <0x1>;
			xlnx,allow-icache-wr = <0x1>;
			xlnx,area-optimized = <0x0>;
			xlnx,branch-target-cache-size = <0x0>;
			xlnx,cache-byte-size = <0x800>;
			xlnx,d-axi = <0x0>;
			xlnx,d-lmb = <0x1>;
			xlnx,d-plb = <0x1>;
			xlnx,data-size = <0x20>;
			xlnx,dcache-addr-tag = <0x11>;
			xlnx,dcache-always-used = <0x1>;
			xlnx,dcache-byte-size = <0x800>;
			xlnx,dcache-data-width = <0x0>;
			xlnx,dcache-force-tag-lutram = <0x0>;
			xlnx,dcache-interface = <0x0>;
			xlnx,dcache-line-len = <0x4>;
			xlnx,dcache-use-fsl = <0x1>;
			xlnx,dcache-use-writeback = <0x0>;
			xlnx,dcache-victims = <0x0>;
			xlnx,debug-enabled = <0x1>;
			xlnx,div-zero-exception = <0x0>;
			xlnx,dynamic-bus-sizing = <0x1>;
			xlnx,ecc-use-ce-exception = <0x0>;
			xlnx,edge-is-positive = <0x1>;
			xlnx,endianness = <0x0>;
			xlnx,family = "virtex5";
			xlnx,fault-tolerant = <0x0>;
			xlnx,fpu-exception = <0x0>;
			xlnx,freq = <0x5f5e100>;
			xlnx,fsl-data-size = <0x20>;
			xlnx,fsl-exception = <0x0>;
			xlnx,fsl-links = <0x0>;
			xlnx,i-axi = <0x0>;
			xlnx,i-lmb = <0x1>;
			xlnx,i-plb = <0x1>;
			xlnx,icache-always-used = <0x1>;
			xlnx,icache-data-width = <0x0>;
			xlnx,icache-force-tag-lutram = <0x0>;
			xlnx,icache-interface = <0x0>;
			xlnx,icache-line-len = <0x4>;
			xlnx,icache-streams = <0x0>;
			xlnx,icache-use-fsl = <0x1>;
			xlnx,icache-victims = <0x0>;
			xlnx,ill-opcode-exception = <0x0>;
			xlnx,instance = "microblaze_0";
			xlnx,interconnect = <0x1>;
			xlnx,interconnect-m-axi-dc-read-issuing = <0x2>;
			xlnx,interconnect-m-axi-dc-write-issuing = <0x20>;
			xlnx,interconnect-m-axi-dp-read-issuing = <0x1>;
			xlnx,interconnect-m-axi-dp-write-issuing = <0x1>;
			xlnx,interconnect-m-axi-ic-read-issuing = <0x2>;
			xlnx,interconnect-m-axi-ip-read-issuing = <0x1>;
			xlnx,interrupt-is-edge = <0x0>;
			xlnx,mmu-dtlb-size = <0x4>;
			xlnx,mmu-itlb-size = <0x2>;
			xlnx,mmu-tlb-access = <0x3>;
			xlnx,mmu-zones = <0x2>;
			xlnx,number-of-pc-brk = <0x1>;
			xlnx,number-of-rd-addr-brk = <0x0>;
			xlnx,number-of-wr-addr-brk = <0x0>;
			xlnx,opcode-0x0-illegal = <0x0>;
			xlnx,optimization = <0x0>;
			xlnx,pvr = <0x0>;
			xlnx,pvr-user1 = <0x0>;
			xlnx,pvr-user2 = <0x0>;
			xlnx,reset-msr = <0x0>;
			xlnx,sco = <0x0>;
			xlnx,stream-interconnect = <0x0>;
			xlnx,unaligned-exceptions = <0x0>;
			xlnx,use-barrel = <0x0>;
			xlnx,use-branch-target-cache = <0x0>;
			xlnx,use-dcache = <0x1>;
			xlnx,use-div = <0x0>;
			xlnx,use-ext-brk = <0x1>;
			xlnx,use-ext-nm-brk = <0x1>;
			xlnx,use-extended-fsl-instr = <0x0>;
			xlnx,use-fpu = <0x0>;
			xlnx,use-hw-mul = <0x1>;
			xlnx,use-icache = <0x1>;
			xlnx,use-interrupt = <0x1>;
			xlnx,use-mmu = <0x3>;
			xlnx,use-msr-instr = <0x1>;
			xlnx,use-pcmp-instr = <0x1>;
		} ;
	} ;
	mb_plb: plb@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "xlnx,plb-v46-1.05.a", "xlnx,plb-v46-1.00.a", "simple-bus";
		ranges ;
		Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,compound";
			ranges ;
			ethernet@81c00000 {
				compatible = "xlnx,xps-ll-temac-2.03.a", "xlnx,xps-ll-temac-1.00.a";
				device_type = "network";
				interrupt-parent = <&xps_intc_0>;
				interrupts = < 8 2 >;
				llink-connected = <&PIM2>;
				local-mac-address = [ 00 0a 35 ca bb 00 ];
				reg = < 0x81c00000 0x40 >;
				xlnx,avb = <0x0>;
				xlnx,bus2core-clk-ratio = <0x1>;
				xlnx,mcast-extend = <0x0>;
				xlnx,phy-type = <0x1>;
				xlnx,phyaddr = <0x1>;
				xlnx,rxcsum = <0x0>;
				xlnx,rxfifo = <0x1000>;
				xlnx,rxvlan-strp = <0x0>;
				xlnx,rxvlan-tag = <0x0>;
				xlnx,rxvlan-tran = <0x0>;
				xlnx,stats = <0x0>;
				xlnx,temac-type = <0x0>;
				xlnx,txcsum = <0x0>;
				xlnx,txfifo = <0x1000>;
				xlnx,txvlan-strp = <0x0>;
				xlnx,txvlan-tag = <0x0>;
				xlnx,txvlan-tran = <0x0>;
			} ;
		} ;
		IIC_EEPROM: i2c@81600000 {
			compatible = "xlnx,xps-iic-2.03.a", "xlnx,xps-iic-2.00.a";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 9 2 >;
			reg = < 0x81600000 0x10000 >;
			xlnx,clk-freq = <0x5f5e100>;
			xlnx,family = "virtex5";
			xlnx,gpo-width = <0x1>;
			xlnx,iic-freq = <0x186a0>;
			xlnx,scl-inertial-delay = <0x5>;
			xlnx,sda-inertial-delay = <0x5>;
			xlnx,ten-bit-adr = <0x0>;
		} ;
		LEDs_8Bit: gpio@81420000 {
			compatible = "xlnx,xps-gpio-2.00.a", "xlnx,xps-gpio-1.00.a";
			reg = < 0x81420000 0x10000 >;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,dout-default = <0x0>;
			xlnx,dout-default-2 = <0x0>;
			xlnx,family = "virtex5";
			xlnx,gpio-width = <0x8>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x0>;
			xlnx,is-dual = <0x0>;
			xlnx,tri-default = <0xffffffff>;
			xlnx,tri-default-2 = <0xffffffff>;
		} ;
		Push_Buttons_5Bit: gpio@81400000 {
			compatible = "xlnx,xps-gpio-2.00.a", "xlnx,xps-gpio-1.00.a";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 10 2 >;
			reg = < 0x81400000 0x10000 >;
			xlnx,all-inputs = <0x1>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,dout-default = <0x0>;
			xlnx,dout-default-2 = <0x0>;
			xlnx,family = "virtex5";
			xlnx,gpio-width = <0x5>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x1>;
			xlnx,is-dual = <0x0>;
			xlnx,tri-default = <0xffffffff>;
			xlnx,tri-default-2 = <0xffffffff>;
		} ;
		RS232_Uart_1: serial@83e00000 {
			clock-frequency = <100000000>;
			compatible = "xlnx,xps-uart16550-3.00.a", "ns16550";
			current-speed = <9600>;
			device_type = "serial";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 11 2 >;
			reg = < 0x83e00000 0x10000 >;
			reg-offset = <0x1003>;
			reg-shift = <2>;
			xlnx,external-xin-clk-hz = <0x17d7840>;
			xlnx,family = "virtex5";
			xlnx,has-external-rclk = <0x0>;
			xlnx,has-external-xin = <0x0>;
			xlnx,is-a-16550 = <0x1>;
		} ;
		SysACE_CompactFlash: sysace@83600000 {
			compatible = "xlnx,xps-sysace-1.01.a", "xlnx,xps-sysace-1.00.a";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 6 2 >;
			reg = < 0x83600000 0x10000 >;
			xlnx,family = "virtex5";
			xlnx,mem-width = <0x10>;
		} ;
		mdm_0: debug@84400000 {
			compatible = "xlnx,mdm-2.00.a";
			reg = < 0x84400000 0x10000 >;
			xlnx,family = "virtex5";
			xlnx,interconnect = <0x1>;
			xlnx,jtag-chain = <0x2>;
			xlnx,mb-dbg-ports = <0x1>;
			xlnx,use-uart = <0x1>;
		} ;
		mpmc@50000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,mpmc-6.02.a";
			ranges ;
			PIM2: sdma@84600100 {
				compatible = "xlnx,ll-dma-1.00.a";
				interrupt-parent = <&xps_intc_0>;
				interrupts = < 4 2 3 2 >;
				reg = < 0x84600100 0x80 >;
			} ;
		} ;
		xps_intc_0: interrupt-controller@81800000 {
			#interrupt-cells = <0x2>;
			compatible = "xlnx,xps-intc-2.01.a", "xlnx,xps-intc-1.00.a";
			interrupt-controller ;
			reg = < 0x81800000 0x10000 >;
			xlnx,kind-of-intr = <0x20>;
			xlnx,num-intr-inputs = <0xc>;
		} ;
		xps_ps2_0: xps-ps2@86a00000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,compound";
			ranges ;
			ranges = < 0x0 0x86a00000 0x10000 >;
			ps2@0 {
				compatible = "xlnx,xps-ps2-1.01.a", "xlnx,xps-ps2-1.00.a";
				interrupt-parent = <&xps_intc_0>;
				interrupts = < 1 2 >;
				reg = < 0x0 0x40 >;
			} ;
			ps2@1000 {
				compatible = "xlnx,xps-ps2-1.01.a", "xlnx,xps-ps2-1.00.a";
				interrupt-parent = <&xps_intc_0>;
				interrupts = < 0 2 >;
				reg = < 0x1000 0x40 >;
			} ;
		} ;
		xps_spi_0: spi@83000000 {
			compatible = "xlnx,xps-spi-2.01.b", "xlnx,xps-spi-2.00.a";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 2 2 >;
			reg = < 0x83000000 0x80 >;
			xlnx,family = "virtex5";
			xlnx,fifo-exist = <0x1>;
			xlnx,num-ss-bits = <0x1>;
			xlnx,num-transfer-bits = <0x8>;
			xlnx,sck-ratio = <0x20>;
		} ;
		xps_tft_0: tft@a0000000 {
			compatible = "xlnx,xps-tft-2.01.a";
			reg = < 0xa0000000 0x10000 >;
			xlnx,dcr-splb-slave-if = <0x1>;
			xlnx,default-tft-base-addr = <0x5f000000>;
			xlnx,family = "virtex5";
			xlnx,i2c-slave-addr = <0x76>;
			xlnx,mplb-awidth = <0x20>;
			xlnx,mplb-dwidth = <0x40>;
			xlnx,mplb-native-dwidth = <0x40>;
			xlnx,mplb-smallest-slave = <0x20>;
			xlnx,tft-interface = <0x1>;
		} ;
		xps_timer_0: timer@83c00000 {
			compatible = "xlnx,xps-timer-1.02.a", "xlnx,xps-timer-1.00.a";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 5 0 >;
			reg = < 0x83c00000 0x10000 >;
			xlnx,count-width = <0x20>;
			xlnx,family = "virtex5";
			xlnx,gen0-assert = <0x1>;
			xlnx,gen1-assert = <0x1>;
			xlnx,one-timer-only = <0x0>;
			xlnx,trig0-assert = <0x1>;
			xlnx,trig1-assert = <0x1>;
		} ;
	} ;
} ;

 

Thank you in advance..

Any help will be really useful... 

 

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Visitor santonop
Visitor
5,032 Views
Registered: ‎02-20-2012

Re: Error compiling kernel virtex 5

I' ve solved the previous error. Now I get the final Image but it seems that the kernel gets in panic  mode for an unknown reason. Can someone help me if I upload the files needed (dts, image file)????

Thank you in advance

Santonop 

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Visitor wzz_gww
Visitor
4,438 Views
Registered: ‎02-18-2013

Re: Error compiling kernel virtex 5

hi,santonp

I got the same problem as you,my kernel also gets in panic.for example,"Oops:kernel get access of bad area,sig:11"

 

could you post you dts and mhs?we can discuss it.

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