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bartokon
Explorer
Explorer
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Registered: ‎09-17-2018

FPGA Manager + Overlays. How to modify pl-custom.dtsi?

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Hi!

I would like to intergrate PYNQ with custom axi-based IP-cores, that needs some modifications in system-user.dtsi

This is system-user.dtsi programmable logic references:

&ZmodADC_0_AXI_ZmodADC1410_1 {
	compatible = "generic-uio";
};

&ZmodDAC_0_AXI_ZmodDAC1411_v1_0_0 {
	compatible = "generic-uio";
};

&amba_pl {
	axidma_chrdev_0: axidma_chrdev@0 {
		compatible = "xlnx,axidma-chrdev";
		dmas = <&ZmodADC_0_axi_dma_0 0>;
		dma-names = "rx_channel";
		index = <0>;
	};

	axidma_chrdev_1: axidma_chrdev@1 {
		compatible = "xlnx,axidma-chrdev";
		dmas = <&ZmodDAC_0_axi_dma_1 0>;
		dma-names = "tx_channel";
		index = <1>;
	};
};

 This is pl.dtsi generated by petalinux 2020.1 (Without fpga manager)

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Sat Sep 19 17:22:26 2020
 */


/ {
	amba_pl: amba_pl {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges ;
		ZmodADC_0_AXI_ZmodADC1410_1: AXI_ZmodADC1410@43c00000 {
			clock-names = "s00_axi_aclk";
			clocks = <&misc_clk_0>;
			compatible = "xlnx,AXI-ZmodADC1410-1.0";
			interrupt-names = "lIrqOut";
			interrupt-parent = <&intc>;
			interrupts = <0 29 4>;
			reg = <0x43c00000 0x10000>;
			xlnx,s00-axi-addr-width = <0x7>;
			xlnx,s00-axi-data-width = <0x20>;
		};
		misc_clk_0: misc_clk_0 {
			#clock-cells = <0>;
			clock-frequency = <50000000>;
			compatible = "fixed-clock";
		};
		ZmodADC_0_axi_dma_0: dma@40400000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_s2mm_aclk";
			clocks = <&misc_clk_0>, <&misc_clk_1>;
			compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
			interrupt-names = "s2mm_introut";
			interrupt-parent = <&intc>;
			interrupts = <0 30 4>;
			reg = <0x40400000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,sg-length-width = <0x10>;
			dma-channel@40400030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 30 4>;
				xlnx,datawidth = <0x20>;
				xlnx,device-id = <0x0>;
			};
		};
		misc_clk_1: misc_clk_1 {
			#clock-cells = <0>;
			clock-frequency = <100000000>;
			compatible = "fixed-clock";
		};
		ZmodDAC_0_AXI_ZmodDAC1411_v1_0_0: AXI_ZmodDAC1411_v1_0@43c10000 {
			clock-names = "s00_axi_aclk";
			clocks = <&misc_clk_0>;
			compatible = "xlnx,AXI-ZmodDAC1411-v1-0-1.0";
			reg = <0x43c10000 0x10000>;
			xlnx,s00-axi-addr-width = <0x7>;
			xlnx,s00-axi-data-width = <0x20>;
		};
		ZmodDAC_0_axi_dma_1: dma@40410000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk";
			clocks = <&misc_clk_0>, <&misc_clk_1>;
			compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
			interrupt-names = "mm2s_introut";
			interrupt-parent = <&intc>;
			interrupts = <0 31 4>;
			reg = <0x40410000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,sg-length-width = <0xe>;
			dma-channel@40410000 {
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0x1>;
				interrupts = <0 31 4>;
				xlnx,datawidth = <0x20>;
				xlnx,device-id = <0x1>;
			};
		};
	};
};

Now I would like to enable the FPGA manager and still have pl.dtsi updated with changes.

I'm moving pl references from system-user.dtsi to pl-cutom.dtsi like this:

This is pl-custom.dtsi after enabling FPGA manager:

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Sat Sep 19 18:38:42 2020
 */


/dts-v1/;
/plugin/;
/ {
	fragment@0 {
		target = <&fpga_full>;
		overlay0: __overlay__ {
			#address-cells = <1>;
			#size-cells = <1>;
			firmware-name = ".bin";
		};
	};
	fragment@1 {
		target = <&amba>;
		overlay1: __overlay__ {
			afi0: afi0@f8008000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "xlnx,afi-fpga";
				reg = <0xF8008000 0x1000>;
				xlnx,afi-width = <0>;
			};
			clocking0: clocking0 {
				#clock-cells = <0>;
				assigned-clock-rates = <100000000>;
				assigned-clocks = <&clkc 15>;
				clock-output-names = "fabric_clk";
				clocks = <&clkc 15>;
				compatible = "xlnx,fclk";
			};
			clocking1: clocking1 {
				#clock-cells = <0>;
				assigned-clock-rates = <100000000>;
				assigned-clocks = <&clkc 16>;
				clock-output-names = "fabric_clk";
				clocks = <&clkc 16>;
				compatible = "xlnx,fclk";
			};
		};
	};
	fragment@2 {
		target = <&amba>;
		overlay2: __overlay__ {
			#address-cells = <1>;
			#size-cells = <1>;
			ZmodADC_0_AXI_ZmodADC1410_1: AXI_ZmodADC1410@43c00000 {
				clock-names = "s00_axi_aclk";
				clocks = <&misc_clk_0>;
				compatible = "xlnx,AXI-ZmodADC1410-1.0";
				interrupt-names = "lIrqOut";
				interrupt-parent = <&intc>;
				interrupts = <0 29 4>;
				reg = <0x43c00000 0x10000>;
				xlnx,s00-axi-addr-width = <0x7>;
				xlnx,s00-axi-data-width = <0x20>;
			};
			misc_clk_0: misc_clk_0 {
				#clock-cells = <0>;
				clock-frequency = <50000000>;
				compatible = "fixed-clock";
			};
			ZmodADC_0_axi_dma_0: dma@40400000 {
				#dma-cells = <1>;
				clock-names = "s_axi_lite_aclk", "m_axi_s2mm_aclk";
				clocks = <&misc_clk_0>, <&misc_clk_1>;
				compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
				interrupt-names = "s2mm_introut";
				interrupt-parent = <&intc>;
				interrupts = <0 30 4>;
				reg = <0x40400000 0x10000>;
				xlnx,addrwidth = <0x20>;
				xlnx,sg-length-width = <0x10>;
				dma-channel@40400030 {
					compatible = "xlnx,axi-dma-s2mm-channel";
					dma-channels = <0x1>;
					interrupts = <0 30 4>;
					xlnx,datawidth = <0x20>;
					xlnx,device-id = <0x0>;
				};
			};
			misc_clk_1: misc_clk_1 {
				#clock-cells = <0>;
				clock-frequency = <100000000>;
				compatible = "fixed-clock";
			};
			ZmodDAC_0_AXI_ZmodDAC1411_v1_0_0: AXI_ZmodDAC1411_v1_0@43c10000 {
				clock-names = "s00_axi_aclk";
				clocks = <&misc_clk_0>;
				compatible = "xlnx,AXI-ZmodDAC1411-v1-0-1.0";
				reg = <0x43c10000 0x10000>;
				xlnx,s00-axi-addr-width = <0x7>;
				xlnx,s00-axi-data-width = <0x20>;
			};
			ZmodDAC_0_axi_dma_1: dma@40410000 {
				#dma-cells = <1>;
				clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk";
				clocks = <&misc_clk_0>, <&misc_clk_1>;
				compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
				interrupt-names = "mm2s_introut";
				interrupt-parent = <&intc>;
				interrupts = <0 31 4>;
				reg = <0x40410000 0x10000>;
				xlnx,addrwidth = <0x20>;
				xlnx,sg-length-width = <0xe>;
				dma-channel@40410000 {
					compatible = "xlnx,axi-dma-mm2s-channel";
					dma-channels = <0x1>;
					interrupts = <0 31 4>;
					xlnx,datawidth = <0x20>;
					xlnx,device-id = <0x1>;
				};
			};
		};
	};
};

I have tried adding this to pl-custom.dtsi:

/ {
    &fragment@2 {
        &overlay2 {        
		&ZmodADC_0_AXI_ZmodADC1410_1 {
			compatible = "generic-uio";
		};

		&ZmodDAC_0_AXI_ZmodDAC1411_v1_0_0 {
			compatible = "generic-uio";
		};

		axidma_chrdev_0: axidma_chrdev@0 {
			compatible = "xlnx,axidma-chrdev";
			dmas = <&ZmodADC_0_axi_dma_0 0>;
			dma-names = "rx_channel";
			index = <0>;
		};

		axidma_chrdev_1: axidma_chrdev@1 {
			compatible = "xlnx,axidma-chrdev";
			dmas = <&ZmodDAC_0_axi_dma_1 0>;
			dma-names = "tx_channel";
			index = <1>;
		};		
        };
    };
};

 

Could someone give me a hand with this?

How should I modify pl-custom.dtsi?

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1 Solution

Accepted Solutions
bartokon
Explorer
Explorer
1,068 Views
Registered: ‎09-17-2018

If anyone is interested I have used pl.dtsi generated by petalinux and use this: https://github.com/byuccl/PYNQ-PRIO to generate overlay.

View solution in original post

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6 Replies
stephenm
Xilinx Employee
Xilinx Employee
1,104 Views
Registered: ‎09-12-2007

Normally, if you wanted to updated a DT node in Petalinux, you would update this node via the system-user.dtsi. for example:

@yournode{

   update here;

};

 

However, this will not work if the overlay is enabled as this node will not be found. In your case you will have to manually update the pl.dtsi

aravindb
Moderator
Moderator
1,101 Views
Registered: ‎02-07-2018

HI @bartokon 

Please  modify the pl device tree changes by adding into pl-custom.dtsi & we can see that is reflecting in final dtbo file.

you just need to add your changes in project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi file

FPGA Manager will take care of adding this pl-custom.dtsi changes to final dtbo file.

I just enabled this below configurations to enable the Device tree overlay.

Make sure to enable this blow configurations:

petalinux-config

FPGA Manager  ---> 

   [*] Fpga Manager 

petlinux-conig -c kernel

                               Device Drivers  --->

                               *- Device Tree and Open Firmware support  --->

    [*]   Device Tree overlays                                                                          

    [*]   Device Tree Overlay ConfigFS interface                  

                                       

You can see the same changes  are reflecting in dtbo file &  after converting it from  dtbo to dtsi  file using “dtc -I dtb -O dts base.dtbo -o system.dtsi” command

Note: you will not see any custom pl device tree changes added in pl.dtsi file after adding it to pl-custom.dtsi file & build it. you will only see those changes in dtbo file.

 

Thanks & regards

Aravind

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bartokon
Explorer
Explorer
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Registered: ‎09-17-2018

Petalinux is overriding pl.dtsi every time you modify it. You could do "chattr +i" to prevent modifications to this file, but this is not a solution but workaround.

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bartokon
Explorer
Explorer
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Registered: ‎09-17-2018

Yes, all these options are already activated. I'm not sure about: “dtc -I dtb -O dts base.dtbo -o system.dtsi”  because petalinux won't generate base.dtbo (or anything) if build fails!

I think the problem is with pl-custom.dtsi in meta-user, but I'm not sure how can I override properties of these fragments

Could you take a look at this bsp?

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bartokon
Explorer
Explorer
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Registered: ‎09-17-2018

If anyone is interested I have used pl.dtsi generated by petalinux and use this: https://github.com/byuccl/PYNQ-PRIO to generate overlay.

View solution in original post

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stephenm
Xilinx Employee
Xilinx Employee
1,060 Views
Registered: ‎09-12-2007

You can also use the DTC manually:

  • dtc -O dtb -o pl.dtbo -b 0 -@ pl.dtsi

You can get the DTC from git: