As it can be seen in device tree, each GEM uses five clocks, CLK_LPD_LSBUS as pclk, gemX_ref as hclk, gemX_tx, gemX_rx and tsu_clk. I'm trying to fire up a fixed link between two devices using SGMII. Besides that the current implementation of macb driver deals nothing with Xilinx PHY driver, I have found the strange behaviour of the clocks: clocks gemX_ref, gemX_tx and gemX_rx reads with clock rate equals zero, thus the driver initialization fails. I've added some piece of code to the driver and PHY (xpsgtr) driver says that pll is successfully locked to external 125MHz LVDS clock, but I still see zero in gemX_ clocks. Can anyone explain why I see that and how to fix this issue and gets external clocks working in GEM?