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jorlamp
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Participant
2,982 Views
Registered: ‎01-12-2018

GMII2RGMII not working in zc702 board

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Hi,

 

I am trying to make the GMII2RGMII ip core in Vivado 2017.3 work with and Opsero Ethernet board but I am having problems at the time of receiving packets from the net.

 

Here the steps I have made:

 

* First add the gmii_to_rgmii ip core to my design, with PHY Address equal to 8, IDELAYCTRL option checked and Shared Logic in Core included. Here my block design.

 

bd.png

 

* Add xdc constraints,

 

 

create_clock -period 5.000 -name clkin -add [get_nets clkin]
create_clock -period 8.000 -name RGMII_ETH_0_rxc -add [get_ports RGMII_ETH_0_rxc]

set_property IOSTANDARD LVCMOS25 [get_ports RGMII_ETH_0_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports MDIO_ETH_PHY_0_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports MDIO_ETH_PHY_0_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports RESET_ETH_0]
set_property IOSTANDARD LVCMOS25 [get_ports {RGMII_ETH_0_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {RGMII_ETH_0_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {RGMII_ETH_0_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {RGMII_ETH_0_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {RGMII_ETH_0_td[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {RGMII_ETH_0_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {RGMII_ETH_0_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {RGMII_ETH_0_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports RGMII_ETH_0_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports RGMII_ETH_0_txc]
set_property IOSTANDARD LVCMOS25 [get_ports RGMII_ETH_0_rx_ctl]

set_property PACKAGE_PIN J15 [get_ports {RGMII_ETH_0_td[3]}]
set_property PACKAGE_PIN J22 [get_ports {RGMII_ETH_0_td[2]}]
set_property PACKAGE_PIN M21 [get_ports {RGMII_ETH_0_td[0]}]
set_property PACKAGE_PIN J21 [get_ports {RGMII_ETH_0_td[1]}]
set_property PACKAGE_PIN K19 [get_ports RGMII_ETH_0_rxc]
set_property PACKAGE_PIN N17 [get_ports MDIO_ETH_PHY_0_mdc]
set_property PACKAGE_PIN K18 [get_ports MDIO_ETH_PHY_0_mdio_io]
set_property PACKAGE_PIN K15 [get_ports RGMII_ETH_0_tx_ctl]
set_property PACKAGE_PIN M22 [get_ports RGMII_ETH_0_txc]
set_property PACKAGE_PIN K20 [get_ports RGMII_ETH_0_rx_ctl]
set_property PACKAGE_PIN N18 [get_ports RESET_ETH_0]
set_property PACKAGE_PIN K21 [get_ports {RGMII_ETH_0_rd[3]}]
set_property PACKAGE_PIN J20 [get_ports {RGMII_ETH_0_rd[2]}]
set_property PACKAGE_PIN L22 [get_ports {RGMII_ETH_0_rd[1]}]
set_property PACKAGE_PIN L21 [get_ports {RGMII_ETH_0_rd[0]}]

* Generate bitstream and export hdf.

* Generate petalinux project for this hdf, add support for Xilinx GMII2RGMII in petalinux kernel, change the system-user.dts whith

 

 

&gem1 {
        local-mac-address = [00 0a 35 00 1e 53];
        phy-handle=<&phy0>;
        gmii2rgmii-phy-handle=<&gmii_to_rgmii_0>;
        phy-mode="gmii";
        status="okay";

        ps7_ethernet_0_mdio: mdio {
                #address-cells = <1>;
                #size-cells = <0>;

                phy0: phy@0 {
                        device_type = "ethernet-phy";
                        reg = <0>;
                };

                gmii_to_rgmii_0: phy@8 {
                        device_type = "ethernet-phy";
                        reg = <8>;
                };
        };
};

 

 

and build it.

 

Once I have BOOT.bin and image.ub deployed in the SD card, from the kernel log I see:

 

 

libphy: mdio_driver_register: xgmiitorgmii
CAN device driver interface
libphy: MACB_mii_bus: probed
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 29 (00:0a:35:00:1e:53)
Marvell 88E1116R e000b000.etherne:07: attached PHY driver [Marvell 88E1116R] (mii_bus:phy_addr=e000b000.etherne:07, irq=-1)
libphy: MACB_mii_bus: probed
macb e000c000.ethernet eth1: Cadence GEM rev 0x00020118 at 0xe000c000 irq 30 (00:0a:35:00:1e:53)
Marvell 88E1510 e000c000.etherne:00: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000c000.etherne:00, irq=-1)

So the Opsero PHY is recognized and xgmiitorgmii is initialized without problems.

 

 

If I bring up the eth1 interface I am having the next log

 

 

root@zc702:~# ifconfig eth1 up
IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
root@zc702:~# macb e000c000.ethernet eth1: unable to generate target frequency: 125000000 Hz
macb e000c000.ethernet eth1: link up (1000/Full)
IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready

 

 

Q: Why eth1 is unable to generate target frequency: 125000000?

 

With ethtool I can see that eth1 speed is defined to 1000 Mb/s

 

root@zc702:~# ethtool eth1
Settings for eth1:
        Supported ports: [ TP MII ]
        Supported link modes:   10baseT/Half 10baseT/Full 
                                100baseT/Half 100baseT/Full 
                                1000baseT/Full 
        Supported pause frame use: No
        Supports auto-negotiation: Yes
        Advertised link modes:  10baseT/Half 10baseT/Full 
                                100baseT/Half 100baseT/Full 
                                1000baseT/Full 
        Advertised pause frame use: No
        Advertised auto-negotiation: Yes
        Link partner advertised link modes:  10baseT/Half 10baseT/Full 
                                             100baseT/Half 100baseT/Full 
                                             1000baseT/Full 
        Link partner advertised pause frame use: No
        Link partner advertised auto-negotiation: No
        Speed: 1000Mb/s
        Duplex: Full
        Port: MII
        PHYAD: 0
        Transceiver: external
        Auto-negotiation: on
        Link detected: yes

And from the TX bytes using ifconfig I can see that there are transmitted packets to the network but not received:

 

eth1      Link encap:Ethernet  HWaddr 00:0A:35:00:1E:53  
          inet6 addr: fe80::20a:35ff:fe00:1e53%lo/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:11 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000 
          RX bytes:0 (0.0 B)  TX bytes:858 (858.0 B)
          Interrupt:30 Base address:0xc000 

I have also enabled the kernel debug and from it I can see

 

root@zc702:~# cat /sys/kernel/debug/clk/clk_summary 
   clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
 ps_clk                                   3            3    33333333          0 0  

.......

          gem1_mux                        0            0   999999990          0 0  
             gem1_div0                    0            0   999999990          0 0  
                gem1_div1                 0            0   124999999          0 0  
          gem0_mux                        1            1   999999990          0 0  
             gem0_div0                    1            1   124999999          0 0  
                gem0_div1                 1            1    25000000          0 0  
                   gem0_emio_mux           1            1    25000000          0 0  
                      gem0                1            1    25000000          0 0  

.........

gem1_emio_mux                            1            1           0          0 0  
    gem1  

I have tried creating a fixed clock in gem1_emio_mux but this makes me not to see any TX packet.

 

I have also tried to patch the kernel like in this link https://www.origin.xilinx.com/support/answers/69132.html but the kernel entry in panic.

 

So my question is, what I am leaving?

I have to put something else in my xdc constraint file?

Is my block design correct?

How can I remove the "eth1 is unable to generate target frequency: 125000000?"

I have to add something else to the device-tree?

 

Thank you very much,

 

Jorge

 

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Accepted Solutions
jorlamp
Participant
Participant
3,468 Views
Registered: ‎01-12-2018

Following this repository https://github.com/fpgadeveloper/ethernet-fmc-zynq-gem I've been able to make the gmii2rgmii working.

 

I have used the build-zedboard.tcl as example and change the zedboard.xdc with this zc720 pins

 

set_property PACKAGE_PIN J18 [get_ports {rgmii_port_1_rd[0]}]       
set_property PACKAGE_PIN K18 [get_ports mdio_io_port_0_mdio_io]     
set_property PACKAGE_PIN M17 [get_ports {rgmii_port_1_rd[2]}]       
set_property PACKAGE_PIN J17 [get_ports mdio_io_port_1_mdio_io]     
set_property PACKAGE_PIN D20 [get_ports rgmii_port_3_rxc]           
set_property PACKAGE_PIN C20 [get_ports rgmii_port_3_rx_ctl]        
set_property PACKAGE_PIN C17 [get_ports {rgmii_port_3_rd[1]}]       
set_property PACKAGE_PIN C18 [get_ports {rgmii_port_3_rd[3]}]       
set_property PACKAGE_PIN N19 [get_ports rgmii_port_1_rxc]           
set_property PACKAGE_PIN N20 [get_ports rgmii_port_1_rx_ctl]        
set_property PACKAGE_PIN N17 [get_ports mdio_io_port_0_mdc]         
set_property PACKAGE_PIN N18 [get_ports reset_port_0]               
set_property PACKAGE_PIN M15 [get_ports {rgmii_port_1_rd[1]}]       
set_property PACKAGE_PIN M16 [get_ports {rgmii_port_1_rd[3]}]       
set_property PACKAGE_PIN R16 [get_ports mdio_io_port_1_mdc]         
set_property PACKAGE_PIN B19 [get_ports rgmii_port_2_rxc]           
set_property PACKAGE_PIN G15 [get_ports {rgmii_port_2_rd[2]}]       
set_property PACKAGE_PIN G16 [get_ports {rgmii_port_2_rd[3]}]       
set_property PACKAGE_PIN F18 [get_ports {rgmii_port_3_rd[0]}]       
set_property PACKAGE_PIN E18 [get_ports {rgmii_port_3_rd[2]}]       
set_property PACKAGE_PIN K19 [get_ports rgmii_port_0_rxc]           
set_property PACKAGE_PIN K20 [get_ports rgmii_port_0_rx_ctl]        
set_property PACKAGE_PIN J20 [get_ports {rgmii_port_0_rd[2]}]       
set_property PACKAGE_PIN K21 [get_ports {rgmii_port_0_rd[3]}]       
set_property PACKAGE_PIN J21 [get_ports {rgmii_port_0_td[1]}]       
set_property PACKAGE_PIN J22 [get_ports {rgmii_port_0_td[2]}]       
set_property PACKAGE_PIN P22 [get_ports {rgmii_port_1_td[0]}]       
set_property PACKAGE_PIN N15 [get_ports {rgmii_port_1_td[2]}]       
set_property PACKAGE_PIN P15 [get_ports {rgmii_port_1_td[3]}]       
set_property PACKAGE_PIN G20 [get_ports rgmii_port_2_rx_ctl]        
set_property PACKAGE_PIN G21 [get_ports {rgmii_port_2_rd[0]}]       
set_property PACKAGE_PIN G17 [get_ports {rgmii_port_2_td[1]}]       
set_property PACKAGE_PIN F17 [get_ports {rgmii_port_2_td[2]}]       
set_property PACKAGE_PIN C15 [get_ports rgmii_port_2_tx_ctl]        
set_property PACKAGE_PIN B15 [get_ports mdio_io_port_2_mdio_io]     
set_property PACKAGE_PIN B17 [get_ports {rgmii_port_3_td[0]}]       
set_property PACKAGE_PIN A16 [get_ports {rgmii_port_3_td[2]}]       
set_property PACKAGE_PIN A17 [get_ports {rgmii_port_3_td[3]}]       
set_property PACKAGE_PIN L21 [get_ports {rgmii_port_0_rd[0]}]       
set_property PACKAGE_PIN L22 [get_ports {rgmii_port_0_rd[1]}]       
set_property PACKAGE_PIN M21 [get_ports {rgmii_port_0_td[0]}]       
set_property PACKAGE_PIN M22 [get_ports rgmii_port_0_txc]           
set_property PACKAGE_PIN J15 [get_ports {rgmii_port_0_td[3]}]       
set_property PACKAGE_PIN K15 [get_ports rgmii_port_0_tx_ctl]        
set_property PACKAGE_PIN R20 [get_ports {rgmii_port_1_td[1]}]       
set_property PACKAGE_PIN R21 [get_ports rgmii_port_1_txc]           
set_property PACKAGE_PIN P20 [get_ports rgmii_port_1_tx_ctl]        
set_property PACKAGE_PIN P21 [get_ports reset_port_1]               
set_property PACKAGE_PIN E19 [get_ports {rgmii_port_2_rd[1]}]       
set_property PACKAGE_PIN E20 [get_ports {rgmii_port_2_td[0]}]       
set_property PACKAGE_PIN F21 [get_ports rgmii_port_2_txc]            
set_property PACKAGE_PIN F22 [get_ports {rgmii_port_2_td[3]}]       
set_property PACKAGE_PIN A21 [get_ports mdio_io_port_2_mdc]         
set_property PACKAGE_PIN A22 [get_ports reset_port_2]               
set_property PACKAGE_PIN D22 [get_ports {rgmii_port_3_td[1]}]       
set_property PACKAGE_PIN C22 [get_ports rgmii_port_3_txc]           
set_property PACKAGE_PIN E21 [get_ports rgmii_port_3_tx_ctl]        
set_property PACKAGE_PIN D21 [get_ports mdio_io_port_3_mdc]         
set_property PACKAGE_PIN B21 [get_ports mdio_io_port_3_mdio_io]     
set_property PACKAGE_PIN L18 [get_ports ref_clk_p]
set_property PACKAGE_PIN L19 [get_ports ref_clk_n]                  
set_property PACKAGE_PIN P16 [get_ports {ref_clk_oe[0]}]            
set_property PACKAGE_PIN J16 [get_ports {ref_clk_fsel[0]}]          
set_property PACKAGE_PIN B22 [get_ports reset_port_3]

Now I can make ping between machines.

View solution in original post

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4 Replies
jorlamp
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Participant
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Registered: ‎01-12-2018

Following this repository https://github.com/fpgadeveloper/ethernet-fmc-zynq-gem I've been able to make the gmii2rgmii working.

 

I have used the build-zedboard.tcl as example and change the zedboard.xdc with this zc720 pins

 

set_property PACKAGE_PIN J18 [get_ports {rgmii_port_1_rd[0]}]       
set_property PACKAGE_PIN K18 [get_ports mdio_io_port_0_mdio_io]     
set_property PACKAGE_PIN M17 [get_ports {rgmii_port_1_rd[2]}]       
set_property PACKAGE_PIN J17 [get_ports mdio_io_port_1_mdio_io]     
set_property PACKAGE_PIN D20 [get_ports rgmii_port_3_rxc]           
set_property PACKAGE_PIN C20 [get_ports rgmii_port_3_rx_ctl]        
set_property PACKAGE_PIN C17 [get_ports {rgmii_port_3_rd[1]}]       
set_property PACKAGE_PIN C18 [get_ports {rgmii_port_3_rd[3]}]       
set_property PACKAGE_PIN N19 [get_ports rgmii_port_1_rxc]           
set_property PACKAGE_PIN N20 [get_ports rgmii_port_1_rx_ctl]        
set_property PACKAGE_PIN N17 [get_ports mdio_io_port_0_mdc]         
set_property PACKAGE_PIN N18 [get_ports reset_port_0]               
set_property PACKAGE_PIN M15 [get_ports {rgmii_port_1_rd[1]}]       
set_property PACKAGE_PIN M16 [get_ports {rgmii_port_1_rd[3]}]       
set_property PACKAGE_PIN R16 [get_ports mdio_io_port_1_mdc]         
set_property PACKAGE_PIN B19 [get_ports rgmii_port_2_rxc]           
set_property PACKAGE_PIN G15 [get_ports {rgmii_port_2_rd[2]}]       
set_property PACKAGE_PIN G16 [get_ports {rgmii_port_2_rd[3]}]       
set_property PACKAGE_PIN F18 [get_ports {rgmii_port_3_rd[0]}]       
set_property PACKAGE_PIN E18 [get_ports {rgmii_port_3_rd[2]}]       
set_property PACKAGE_PIN K19 [get_ports rgmii_port_0_rxc]           
set_property PACKAGE_PIN K20 [get_ports rgmii_port_0_rx_ctl]        
set_property PACKAGE_PIN J20 [get_ports {rgmii_port_0_rd[2]}]       
set_property PACKAGE_PIN K21 [get_ports {rgmii_port_0_rd[3]}]       
set_property PACKAGE_PIN J21 [get_ports {rgmii_port_0_td[1]}]       
set_property PACKAGE_PIN J22 [get_ports {rgmii_port_0_td[2]}]       
set_property PACKAGE_PIN P22 [get_ports {rgmii_port_1_td[0]}]       
set_property PACKAGE_PIN N15 [get_ports {rgmii_port_1_td[2]}]       
set_property PACKAGE_PIN P15 [get_ports {rgmii_port_1_td[3]}]       
set_property PACKAGE_PIN G20 [get_ports rgmii_port_2_rx_ctl]        
set_property PACKAGE_PIN G21 [get_ports {rgmii_port_2_rd[0]}]       
set_property PACKAGE_PIN G17 [get_ports {rgmii_port_2_td[1]}]       
set_property PACKAGE_PIN F17 [get_ports {rgmii_port_2_td[2]}]       
set_property PACKAGE_PIN C15 [get_ports rgmii_port_2_tx_ctl]        
set_property PACKAGE_PIN B15 [get_ports mdio_io_port_2_mdio_io]     
set_property PACKAGE_PIN B17 [get_ports {rgmii_port_3_td[0]}]       
set_property PACKAGE_PIN A16 [get_ports {rgmii_port_3_td[2]}]       
set_property PACKAGE_PIN A17 [get_ports {rgmii_port_3_td[3]}]       
set_property PACKAGE_PIN L21 [get_ports {rgmii_port_0_rd[0]}]       
set_property PACKAGE_PIN L22 [get_ports {rgmii_port_0_rd[1]}]       
set_property PACKAGE_PIN M21 [get_ports {rgmii_port_0_td[0]}]       
set_property PACKAGE_PIN M22 [get_ports rgmii_port_0_txc]           
set_property PACKAGE_PIN J15 [get_ports {rgmii_port_0_td[3]}]       
set_property PACKAGE_PIN K15 [get_ports rgmii_port_0_tx_ctl]        
set_property PACKAGE_PIN R20 [get_ports {rgmii_port_1_td[1]}]       
set_property PACKAGE_PIN R21 [get_ports rgmii_port_1_txc]           
set_property PACKAGE_PIN P20 [get_ports rgmii_port_1_tx_ctl]        
set_property PACKAGE_PIN P21 [get_ports reset_port_1]               
set_property PACKAGE_PIN E19 [get_ports {rgmii_port_2_rd[1]}]       
set_property PACKAGE_PIN E20 [get_ports {rgmii_port_2_td[0]}]       
set_property PACKAGE_PIN F21 [get_ports rgmii_port_2_txc]            
set_property PACKAGE_PIN F22 [get_ports {rgmii_port_2_td[3]}]       
set_property PACKAGE_PIN A21 [get_ports mdio_io_port_2_mdc]         
set_property PACKAGE_PIN A22 [get_ports reset_port_2]               
set_property PACKAGE_PIN D22 [get_ports {rgmii_port_3_td[1]}]       
set_property PACKAGE_PIN C22 [get_ports rgmii_port_3_txc]           
set_property PACKAGE_PIN E21 [get_ports rgmii_port_3_tx_ctl]        
set_property PACKAGE_PIN D21 [get_ports mdio_io_port_3_mdc]         
set_property PACKAGE_PIN B21 [get_ports mdio_io_port_3_mdio_io]     
set_property PACKAGE_PIN L18 [get_ports ref_clk_p]
set_property PACKAGE_PIN L19 [get_ports ref_clk_n]                  
set_property PACKAGE_PIN P16 [get_ports {ref_clk_oe[0]}]            
set_property PACKAGE_PIN J16 [get_ports {ref_clk_fsel[0]}]          
set_property PACKAGE_PIN B22 [get_ports reset_port_3]

Now I can make ping between machines.

View solution in original post

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zhangjiali
Visitor
Visitor
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Registered: ‎04-18-2018

Hi, @jorlamp

I have the same question about using gmii2rgmii.

I following the https://github.com/fpgadeveloper/ethernet-fmc-zynq-gem, patch the kernel & add the devicetree

but still get the error, and can't get a dhcp address:

 

Configuring network interfaces... IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc (v1.24.1) started
Sending discover...
macb e000b000.ethernet eth0: unable to generate target frequency: 25000000 Hz
macb e000b000.ethernet eth0: link up (100/Full)
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
Sending discover...
Sending discover...
No lease, forking to background

 

anything else should be attention? and how did you fix the error.

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jorlamp
Participant
Participant
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Registered: ‎01-12-2018

For me this constraints were useful

 

create_clock -period 8.000 -name ETH_RGMII_0_rxc -waveform {0.000 4.000} [get_ports ETH_RGMII_0_rxc]

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells -hier -filter {name =~ *_i/gmii_to_rgmii_0/U0/*_gmii_to_rgmii_0_0_core/*delay_rgmii_rxd*}]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *_i/gmii_to_rgmii_0/U0/*_gmii_to_rgmii_0_0_core/*delay_rgmii_rxd*}]


set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells *_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/*_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells *_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/*_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl]

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells *_i/gmii_to_rgmii_0/U0/i_*_gmii_to_rgmii_0_0_idelayctrl]
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binbinyantai
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Registered: ‎09-12-2017

do you find the solution about this problems?

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