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sshoaf
Adventurer
Adventurer
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Registered: ‎06-13-2011

Help adding bitstream to Zynq boot image

Now that I have a PS running Linux using the 14.2 release as a base, I want to add some PL.  I am looking at the Zynq-7000 EPP Software Developers Guide (UG821 v2.0) in section 3.5 on Boot Image Creation, and have a question.  It shows (pg 26) the format of the BIF file as follows,

 

the_ROM_image:

{

[init]init_data.int

[bootloader]myDesign.elf

Partition1.bit

Partition1.rbt

Partition2.elf

Partition3.elf

}

 

What is the Partition1.rbt file?  The software developers guide says it gets created by Bitgen, but the file doesn't appear to get created for the ZC702 system template that I used in EDK as a base for the PS.  The EDK system synthesized and implemented without errors in PlanAhead.  I was also able to generate the bitstream.  Now I need to figure out how to create a correct BOOT.bin file and then have the FSBL program it into the PL.

 

Thanks,

 

Steve

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norman_wong
Scholar
Scholar
4,614 Views
Registered: ‎05-28-2012

I haven't used .int or .rbt file yet I did not know I had to. In your QSPI thread, I see that you have built the boot.bin from your own FSBL and u-boot.elf. You should be able to add your PL as .bit file. Just put it between the FSBL and u-boot in the .bif file. Images are loaded in the order specified in the .bif. ROM loader loads the FSBL first. The FSBL will know to load the .bit file into the FPGA. Then load U-boot.

 

Never quite clear in all the docs what was the Xilinx design intent. Here's what I am guessing. Stuff you probably already know. The SDK workspace consists of:

1) Hardware Platform Project

This project "points" to the EDK's SDK Export directory. The file in the SDK Export directory are automatically copied into this project. A lot of files are copied but only three are used in this workspace. One is the custom named bitsream .bit file. It gets renamed to system.bit. The other two file is ps7_init.c and .h files.

2) BSP Project

Suppose to provide Board Support Package code for use by FSBL. On 14.1, the FSBL has it's own FSBL code and this project can be removed. Maybe the 14.2 FSBL uses the BSP.

3) FSBL Project

Autogenerated FSBL code. As part of the build process, it automatically copies over ps7_init.c and ps7_init.h from the Hardware Platform project. The ps7_init code setups the HW, DDR clock, MIO, etc. as specified in the EDK. If you have changed the PS in the EDK, these files is where the changes show up.

 

 

 

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sshoaf
Adventurer
Adventurer
4,559 Views
Registered: ‎06-13-2011

Norman,

 

I was able to get the bitstream added to the Zynq boot image and successfully boot the system from QSPI.  As you said in the QSPI thread, there is only 1 MB of space reserved in the QSPI memory map in the current (version 14.2) Zynq release for the bitstream.  The size of the bitstream is 3.85 MB so I had to move the memory map around in U-Boot for the QSPI boot portion and recompile it.  I turned on the debug printing in XIlinx's default FSBL project and confirmed that the system was booting from QSPI and that it successfully downloaded the bitstream.

 

Thanks for all of your help with my posts,

 

Steve

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