11-05-2015 02:19 AM
i tried to optimize the emmc card speed of a Z7010 Design.
currently we use kernel 3.14.2 xlnx and sdio clock set to 125Mhz
the actual EMMC frequency is set to 31.25 Mhz which is 125Mhz/4
my goal is to set the actual EMMC frequency to 50Mhz which could be 100Mhz/2
but setting the sdio clock to 100Mhz in the vivado design and changing the device tree
entry for sdio clock to 100Mhz does not change anything. The actual clock is shown as 31.25Mhz !?
Where does the clock subsystem get the values for the sdio clock from ? Is the divisor of sdio clock
setable per device tree ?
11-05-2015 04:29 AM
The divisor is calculated at runtime, and limited. If the card reports 50MHz as max rate, the clock will be set to max value below that. With a 125MHz base clock, the "/4" option is the "best" solution.
Things to know:
- The clock frequency is NOT part of the bitstream. It is set by the bootloader. To activate the settings, create a new bootloader.
- If your kernel has "debugfs" enabled, you can see all clocks in /sys/kernel/debug/clk/clk_summary.
- Vivado will do "strange things". I often found that only setting all the multipliers/dividers manually would give me what I wanted. There's a tab page to do that in the PS configuration screens.