08-18-2017 11:42 AM
I am running some experiments on the Ultrascale+ board running Petalinux and we suspect that the width of the DDR port configured by Linux is causing us some problem. Is it possible to change the width of the port from inside Linux ?
08-24-2017 09:56 AM
You would need to change this in the Vivado and re-export,and then regenerate the bootloader.
08-30-2017 12:39 PM
I could check that the information is correctly exported in the HDF file, however, the behavior in Petalinux seems to indicate that the bus is not properly configured. Please see below a snippet of code from the HDF:
<PARAMETER NAME="C_MAXIGP0_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_MAXIGP1_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_SAXIGP0_DATA_WIDTH" VALUE="64"/>
<PARAMETER NAME="C_SAXIGP1_DATA_WIDTH" VALUE="128"/>
Do you have any suggestion on how to check whether Linux is, in fact, using this configuration?
08-31-2017 09:56 AM
The parameters listed here are IMHO not related to the DDR port, well at least not directly related.
C_MAXIGP0_DATA_WIDTH and C_MAXIGP1_DATA_WIDTH specify the data width of the two AXI General Purpose Master ports, and C_SAXIGP0_DATA_WIDTH and C_SAXIGP1_DATA_WIDTH the data width of the two AXI General Purpose Slave ports.
Hope this clarifies,
08-31-2017 12:31 PM
08-31-2017 01:36 PM
thanks for answering.
Now the problem is how can we pack the changed init_psu* files again into a HDF file ...
Why not modify the HDF file directly?
08-31-2017 01:40 PM
08-31-2017 01:56 PM