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Registered: ‎10-02-2018

How to disable cache in linux on zc706?

Hi, I'm run cdma in petalinux on zc706. I 'm convert driver cdma from standalone to linux.

But i don't know how to disable cache in petalinux.


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Registered: ‎02-07-2018

HI @sonminh 

Can you please refer this link :

Hope this should help you.


Thanks & regards


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Registered: ‎10-02-2018

Hi @aravindb ,

Folow link you shared, I just try implement as you talk but no have any change once boot petalinux 2017.4 on zc706:

1. In file xilinx_zynq_defconfig of external linux  (components/ext_sources/linux-xlnx-2017.4_video_ea/arch/arm/configs), I add in to end of file:


2. petalinux-config -c kernel --defconfig xilinx_zynq_defconfig 

3. petalinux-build -c kernel

4. Modify file system-user.dtsi in /project-spec/meta-user/recipes-bsp/device-tree/files:

/include/ "system-conf.dtsi"
/ {
&amba {
cache-controller@f8f02000 {
status = "disabled";

5. Petalinux-build

This is my device-tree after disable cache and build:

cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-level = <0x2>;
status = "disabled";

But once boot with BOOT.bin and image.ub just build, L2 cache still enable and I don't know veryfy that L1 is disabled. I see time to boot still fast. Here is console once boot linux, L2 cache still probe although disable.

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Linux version 4.9.0-xilinx (thanhnt@ubuntu) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 SMP PREEMPT Sat Nov 16 14:11:29 +07 2019
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5287d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt:Machine model: Zynq ZC706 Development Board
bootconsole [earlycon0] enabled
cma: Reserved 16 MiB at 0x3f000000
Memory policy: Data cache writealloc
percpu: Embedded 14 pages/cpu @ef7cb000 s25932 r8192 d23220 u57344
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260608
Kernel command line: console=ttyPS0,115200 earlyprintk
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1007240K/1048576K available (6144K kernel code, 200K rwdata, 1464K rodata, 1024K init, 230K bss, 24952K reserved, 16384K cma-reserved, 245760K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0700000   (7136 kB)
      .init : 0xc0900000 - 0xc0a00000   (1024 kB)
      .data : 0xc0a00000 - 0xc0a32180   ( 201 kB)
       .bss : 0xc0a32180 - 0xc0a6b998   ( 231 kB)
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
efuse mapped to f0802000
slcr mapped to f0804000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at f0804100
Zynq clock init

 Can you talk clearly?

Thank you.

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