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Explorer
Explorer
2,180 Views
Registered: ‎11-21-2013

How to run 2 arm cores at 800MHz in ZC706 linaro linux?

Dear All,

 

I generate the hw by setting the arm cpu clock frequency to 800MHz, and the devicetree.dtb also includes this information (0xc3500  is 800Mhz)

 

 cpu@0 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <0x0>;
                        clocks = <0x1 0x3>;
                        clock-latency = <0x3e8>;
                        cpu0-supply = <0x2>;
                        operating-points = <0xc3500 0xf4240 0x51616 0xf4240>;
                };

 

Now i try to get the clk frequency in linux on ZC706, and all i get is this output below, it can be seen that the fclk0 is 100 MHz, and fclk1 is 200 Mhz, and all these are correct.

However, the arm cpu clock cpu_6or4x   is not 800 Mhz, but the default one 666Mhz

 

Any ideas?

 

analog@analog:~$ cat /sys/kernel/debug/clk/clk_summary
cat: /sys/kernel/debug/clk/clk_summary: Permission denied
analog@analog:~$ sudo cat /sys/kernel/debug/clk/clk_summary
   clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
 clock-generator                          0            0   148499999          0 0  
 ps_clk                                   3            3    33333333          0 0  
    iopll_int                             1            1   999999990          0 0  
       iopll                             10           10   999999990          0 0  
          dbg_mux                         1            1   999999990          0 0  
             dbg_div                      1            1    66666666          0 0  
                dbg_emio_mux              1            1    66666666          0 0  
                   dbg_trc                1            1    66666666          0 0  
          can_mux                         0            0   999999990          0 0  
             can_div0                     0            0    40000000          0 0  
                can_div1                  0            0     8000000          0 0  
                   can1_gate              0            0     8000000          0 0  
                      can1                0            0     8000000          0 0  
                   can0_gate              0            0     8000000          0 0  
                      can0                0            0     8000000          0 0  
          gem1_mux                        0            0   999999990          0 0  
             gem1_div0                    0            0    16666667          0 0  
                gem1_div1                 0            0    16666667          0 0  
                   gem1_emio_mux           0            0    16666667          0 0  
                      gem1                0            0    16666667          0 0  
          gem0_mux                        1            1   999999990          0 0  
             gem0_div0                    1            1   124999999          0 0  
                gem0_div1                 1            1   124999999          0 0  
                   gem0_emio_mux           1            1   124999999          0 0  
                      gem0                1            1   124999999          0 0  
          spi0_mux                        0            0   999999990          0 0  
             spi0_div                     0            0    15873016          0 0  
                spi1                      0            0    15873016          0 0  
                spi0                      0            0    15873016          0 0  
          uart0_mux                       1            1   999999990          0 0  
             uart0_div                    1            1    50000000          0 0  
                uart1                     1            1    50000000          0 0  
                uart0                     0            0    50000000          0 0  
          sdio0_mux                       1            1   999999990          0 0  
             sdio0_div                    1            1    50000000          0 0  
                sdio1                     0            0    50000000          0 0  
                sdio0                     1            1    50000000          0 0  
          pcap_mux                        1            1   999999990          0 0  
             pcap_div                     1            1   199999998          0 0  
                pcap                      1            2   199999998          0 0  
          lqspi_mux                       1            1   999999990          0 0  
             lqspi_div                    1            1   199999998          0 0  
                lqspi                     1            1   199999998          0 0  
          fclk3_mux                       1            1   999999990          0 0  
             fclk3_div0                   1            1    50000000          0 0  
                fclk3_div1                1            1    50000000          0 0  
                   fclk3                  1            1    50000000          0 0  
          fclk2_mux                       1            1   999999990          0 0  
             fclk2_div0                   1            1    50000000          0 0  
                fclk2_div1                1            1    50000000          0 0  
                   fclk2                  1            1    50000000          0 0  
          fclk1_mux                       1            1   999999990          0 0  
             fclk1_div0                   1            1   199999998          0 0  
                fclk1_div1                1            1   199999998          0 0  
                   fclk1                  1            1   199999998          0 0  
          fclk0_mux                       1            1   999999990          0 0  
             fclk0_div0                   1            1    99999999          0 0  
                fclk0_div1                1            1    99999999          0 0  
                   fclk0                  1            1    99999999          0 0  
    ddrpll_int                            1            1  1066666656          0 0  
       ddrpll                             3            3  1066666656          0 0  
          dci_div0                        1            1    30476191          0 0  
             dci_div1                     1            1    10158731          0 0  
                dci                       1            1    10158731          0 0  
          ddr3x_div                       1            1   533333328          0 0  
             ddr3x                        1            1   533333328          0 0  
          ddr2x_div                       1            1   355555552          0 0  
             ddr2x                        1            1   355555552          0 0  
    armpll_int                            1            1  1333333320          0 0  
       armpll                             1            1  1333333320          0 0  
          smc_mux                         0            0  1333333320          0 0  
             smc_div                      0            0    22222222          0 0  
                smc                       0            0    22222222          0 0  
          cpu_mux                         1            1  1333333320          0 0  
             cpu_div                      3            3   666666660          0 0  
                cpu_1x_div                1            1   111111110          0 0  
                   cpu_1x                10           10   111111110          0 0  
                      smc_aper            0            0   111111110          0 0  
                      lqspi_aper           1            1   111111110          0 0  
                      gpio_aper           1            1   111111110          0 0  
                      uart1_aper           1            1   111111110          0 0  
                      uart0_aper           0            0   111111110          0 0  
                      i2c1_aper           0            0   111111110          0 0  
                      i2c0_aper           1            1   111111110          0 0  
                      can1_aper           0            0   111111110          0 0  
                      can0_aper           0            0   111111110          0 0  
                      spi1_aper           0            0   111111110          0 0  
                      spi0_aper           0            0   111111110          0 0  
                      sdio1_aper           0            0   111111110          0 0  
                      sdio0_aper           1            1   111111110          0 0  
                      gem1_aper           0            0   111111110          0 0  
                      gem0_aper           1            1   111111110          0 0  
                      usb1_aper           0            0   111111110          0 0  
                      usb0_aper           0            0   111111110          0 0  
                      dbg_apb             1            1   111111110          0 0  
                      swdt                1            1   111111110          0 0  
                cpu_2x_div                1            1   222222220          0 0  
                   cpu_2x                 1            2   222222220          0 0  
                      dma                 0            1   222222220          0 0  
                cpu_3or2x_div             1            1   333333330          0 0  
                   cpu_3or2x              2            2   333333330          0 0  
                cpu_6or4x                 0            0   666666660          0 0  
 can1_mio_mux                             0            0           0          0 0  
 can0_mio_mux                             0            0           0          0 0

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1 Reply
Explorer
Explorer
2,068 Views
Registered: ‎11-21-2013

Re: How to run 2 arm cores at 800MHz in ZC706 linaro linux?

New question,

 

According to this post:

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-PS-clock-speed-on-ZC706/td-p/354197?db=5

 

> I generate new .bit file

>I generate the fsbl.elf through SDK or HSI from Xilinx wiki,

>then i replaced the default FSBL file inside the zynq-zc706-adv7511/bootgen_sysfiles.tgz

>  and generate boot.in file.  Well,  the ZC706 now cannot even run the first stage boot loader, cause the uart output terminal has nothing.

 

I think the problem is that i generated the fsbl using a newer version of SDK which came with gcc 4.9, the default is with 4.8?  I print out the strings output into the below two log files

 

There is also another post about .bit file and u-boot version mismatch:

https://ez.analog.com/thread/83542

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