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Participant jrceokura
Participant
122 Views
Registered: ‎07-17-2018

I can't write PL IP register.

Hi all!

I'm a software guy. I use customboard based on ZC706.

I got a hdf file and bit file from FPGA developer.

pl.dtsi is below.


--------
        mytest_slave_0: mytest_slave@60000000 {
            compatible = "xlnx,mytest-slave-1.0";
            reg = <0x60000000 0x10000>;
        };
--------
 


My mission is IP's setting on Linux.
But I can't do it.
I tried below, but all try is failed.
1. on the U-boot, I use md and mw command.
2. on the Linux, I use devmem command.
3. on the Linux, I use custom app that I create.

Do you know what to do?

 

Then,FPGA developer said that his bare metal application can do it.

I got bare metal application driver source. but I can' t build it.

The source is below. it was contained in components\plnx_workspace\device-tree\device-tree-generation\drivers

I think that it is only use on fsbl.

 

--------

#define MYTEST_SLAVE_mWriteReg(BaseAddress, RegOffset, Data) \
    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))

#define MYTEST_SLAVE_mReadReg(BaseAddress, RegOffset) \
    Xil_In32((BaseAddress) + (RegOffset))
--------

 


3's detail is below.

I created app for write value.
This app use /dev/uio0.
And I modified system-user.dtsi below.
--------
        mytest_slave@60000000 {
            compatible = "generic-uio";
            reg = <0x60000000 0x10000>;
        };
--------
 
I checked that /sys/class/uio/uio0/maps/map0 is OK.
# cat /sys/class/uio/uio0/maps/map0/name
/amba_pl/mytest_slave@60000000
# cat /sys/class/uio/uio0/maps/map0/addr
0x60000000

Thank you!

0 Kudos
6 Replies
Moderator
Moderator
104 Views
Registered: ‎09-12-2007

Re: I can't write PL IP register.

It is not clear from your description. What do you see if you do a devmem addr?  where the addr is the 0x60000000 + offset

There is some example here on using the UIO:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842490/Testing+UIO+with+Interrupt+on+Zynq+Ultrascale

 

Highlighted
95 Views
Registered: ‎07-23-2019

Re: I can't write PL IP register.

Are the memory addresses of that PL peripheral correctly mapped?

One reason could be you copied a design from somebody else, auto-generated the addresses, don't match, and voila...

Moderator
Moderator
90 Views
Registered: ‎09-12-2007

Re: I can't write PL IP register.

If you have the HDF, you can verify the address map of your IP in XSCT

hsi::open_hw_design you_hdf_file.hdf

common::report_property hsi::get_cells mytest_slave_0

You will see the base address here

hsi::close_hw_design [hsi::current_hw_design]

to close

Participant jrceokura
Participant
64 Views
Registered: ‎07-17-2018

Re: I can't write PL IP register.

Hi stephenm!

Thank you for your reply. and I'm sorry for my not clear descripotion.

I did below command and got output.

I write the data. But I can't read the data.

--------

# /sbin/devmem 0x600041B0 32
0x00000000

# /sbin/devmem 0x600041B0 32 0xFFFFFFFF

# /sbin/devmem 0x600041B0 32
0x00000000

--------

 

On U-Boot,

--------

Zynq> mw.l 600041B0 FFFFFFFF
Zynq> md.l 600041B0
600041b0: 00000000 00000000 00000000 00000000 ................
600041c0: 00000000 00000000 00000000 00000000 ................
600041d0: 00000000 00000000 00000000 00000000 ................
600041e0: 00000000 00000000 00000000 00000000 ................
600041f0: 00000000 00000000 00000000 00000000 ................
60004200: 00000000 00000000 00000000 00000000 ................
60004210: 00000000 00000000 00000000 00000000 ................
60004220: 00000000 00000000 00000000 00000000 ................
60004230: 00000000 00000000 00000000 00000000 ................
60004240: 00000000 00000000 00000000 00000000 ................
60004250: 00000000 00000000 00000000 00000000 ................
60004260: 00000000 00000000 00000000 00000000 ................
60004270: 00000000 00000000 00000000 00000000 ................
60004280: 00000000 00000000 00000000 00000000 ................
60004290: 00000000 00000000 00000000 00000000 ................
600042a0: 00000000 00000000 00000000 00000000 ................

--------

Thank you!

0 Kudos
Participant jrceokura
Participant
55 Views
Registered: ‎07-17-2018

Re: I can't write PL IP register.

Hi  archangel-lightworks!   Hi stephenm!

I checked HDF. The result is below.

I think that it is not wrong.

If you notice anything, Could you teach me?

--------

xsct% common::report_property [hsi::get_cells mytest_slave_0]
Property Type Read-only Value
ADDRESS_TAG string true
CLASS string true cell
CONFIG.C_S_AXI_ADDR_WIDTH string true 32
CONFIG.C_S_AXI_BASEADDR string true 0x60000000
CONFIG.C_S_AXI_DATA_WIDTH string true 32
CONFIG.C_S_AXI_HIGHADDR string true 0x6000FFFF
CONFIG.Component_Name string true ??????_mytest_slave_0_0
CONFIG.EDK_IPTYPE string true PERIPHERAL
CONFIGURABLE bool true 0
DRIVER_MODE string true
HIER_NAME string true mytest_slave_0
IP_NAME string true mytest_slave
IP_TYPE enum true PERIPHERAL
IS_HIERARCHICAL bool true 0
IS_PL bool true 1
NAME string true mytest_slave_0
PRODUCT_GUIDE string true
SLAVES string* true
VLNV string true ???:user:mytest_slave:1.0

--------

! I changed the personal infomation to ? !

 

Thank you.

0 Kudos
34 Views
Registered: ‎07-23-2019

Re: I can't write PL IP register.

 

Reasons could be that peripheral or some other part of your OS is overwriting you. Is that AXI peripheral custom? In that case you know where it writes to.