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Visitor
Visitor
3,372 Views
Registered: ‎07-11-2011

ICAP read stalls and disconnects MicroBlaze

Hello,

 

I'm trying to read-back the captured state of my Virtex-6 FPGA mounted on the ML-605 board. I'm trying to read this configuration via the ICAP AXI module in combination with the ICAP Linux driver. I've set the ICAP Fifo size to 256 for both the read and write FIFO as stated in the datasheet. 

 

I've updated the Linux driver for the Virtex-6 by adding the correct configuration register and the assignment of this register. 

static const struct config_registers v6_config_registers = {

       .CRC = 0,

       .FAR = 1,

       .FDRI = 2,

       .FDRO = 3,

       .CMD = 4,

       .CTL = 5,

       .MASK = 6,

       .STAT = 7,

       .LOUT = 8,

       .COR = 9,

       .MFWR = 10,

       .FLR = UNIMPLEMENTED,

       .KEY = UNIMPLEMENTED,

       .CBC = 11,

       .IDCODE = 12,

       .AXSS = 13,

       .C0R_1 = 14,

       .CSOB = 15,

       .WBSTAR = 16,

       .TIMER = 17,

       .BOOTSTS = 22,

       .CTL_1 = 24,

};

and

} else if (!strcmp(family, "virtex6")) {

              regs = &v6_config_registers;

 

I connect to the board using the Xilinx SDK -> XDS console. I program the board with my bit-file and then load Linux using the dow command. Linux boots and all goes well here. 

 

Using a litte program I've written I've opened the \dev\icap0 device node and start writing commands to this components. I cannot use the ICAP read-back sequence from the datasheet directly since this shuts down the FPGA. This stops the Microblaze and results in a failure.

 

The program I've written is able to readback exacly 7055 configuration words and then the program hangs and XDS debugger disconnects. 

 

- Does anyone have any idea what could be going wrong?

 

The command sequence I use to perform the readback is;

    0xffffffff    // Packet::Dummy,
    0x000000BB,   // Bus width sync
    0x11220044,   // bus width detect
    0xffffffff    // Packet::Dummy,
    0xaa995566    // Packet::Sync,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x30008001    // ( ( 1 << 29 ) | ( 4 << 13 ) | ( 2 << 27 ) | 1 ),
    0x00000004    // Packet::Rcfg,
    0x20000000    // Packet::Noop,
    0x30002001,   // Type 2 packet to write FAR in next packet
    0x00000000,   // FAR = 0
    0x28006000,   // 001 01 RRRRRRRRRxxxxx RR 0 TYPE 1
    0x48000000 + ( 147600 ), // 010 RR 147600 TYPE 2
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,
    0x20000000    // Packet::Noop,

 

After this sequence I start reading 147600 configuration words from the read FIFO. After printing 7055 words the program jumps to undefined memory (I think). 

 

Thanks,

 

Luke

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2 Replies
Highlighted
Scholar
Scholar
3,366 Views
Registered: ‎02-27-2008

Luke,

 

There is only one configuration interface, so the JTAG used fo rthe debugger can't be running at the same time you are trying to use ICAP.  JTAG will have priority, and ICAp will wait (forever).


Also, reading back BRAM contents while they are being used may result in their contents being corrupted.  BRAM have only two ports, A, and B, so when ICAP reads a BRAM it also takes away the A port, and if the BRAM is being clocked on either the A or B ports, addressed contents can be trashed.


To safely capture everything, one needs to stop all clocks, and then readback, and then restart clocks.  Very hard to do using ICAP (can not be done:  you have to restrict using ICAP to only the frames which have their clocks stopped to be perfectly safe).



Austin Lesea
Principal Engineer
Xilinx San Jose
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Highlighted
Visitor
Visitor
3,361 Views
Registered: ‎07-11-2011

Hello Austin,

 

Thank you for you quick response.

 

There is only one configuration interface, so the JTAG used for the debugger can't be running at the same time you are trying to use ICAP.

Ok! I already assumed this would be the case. For that reason I disconnected XDS after downloading Linux "disconnect 0". But this generates exactly the same behavior. Is it enough to just simply disconnect the JTAG connection or do I need to close the SDK and disconnect the USB cable?

 

To safely capture everything, one needs to stop all clocks…perfectly safe).

I'm aware of the BRAM limitation, only I thought that the readback would not include BRAM content since I'm not reading BlockType 001 (in the FAR register). The idea was to read-back the entire FPGA logic except BRAM content and then manually read the relevant BRAMs which have their clocks disabled. The CAPTURE_VIRTEX6 can always be enabled right?  This has nothing to do with the read-back limitation.

 

I'm only interested to capture sub-part of my design. The MicroBlaze is only introduced as a monitoring unit of a stand-alone design. 

 

Luke

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