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James_Edgar
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Registered: ‎08-24-2020

Include pl_mem in dtso file

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I have modified the SSR project for the ZCU111 board to use one of the high frequency ADC/DAC channels instead of the default channels which are low frequency.  I generated an .xsa file from Vivado and then used petalinux commands:

petalinux-build -c device-tree -x cleanstate
petalinux-build -c device-tree

to generate a .dtbo file.

When I tried loading the .bin and .dtbo file, none of the /sys/class/plmem/plmem0-15 drivers were installed.  I converted the .dtbo file to a .dtsi file, and all of these references were missing.

I have tried editing the .dtsi file by hand to add these back in, but have not been successful.  Fourteen of the 16 plmem folders are created, but 0 and 8 are always missing, and there are driver creation errors.

Before pursuing this further, I wanted to find out if there was a more efficient way to do this. 

Should I expect the .dtso file generated from the .xsa file to automatically include the plmem sections?  I am using the ZCU111 board files in the project.

If not, are there instructions as to how to correctly add these?  There seem to be a couple of layers involved, and creating them by hand with references between plmem, dma, and sram pool phandles seems like an error prone solution.

Thanks,

James

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aravindb
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Registered: ‎02-07-2018

Hi @James_Edgar 

You can modify pl device tree changes using pl-custom.dtsi file. so that after building it this changes will reflect in base.dtbo file.

Below is for your reference

/ {
fragment@2 {
target = <&amba_pl>;
overlay2: __overlay__ {

ethernet@a0100000 {
axistream-connected = <0x45>;
axistream-control-connected = <0x45>;

};
dma@a0010000 {
linux,phandle = <0x45>;
phandle = <0x45>;
};

axi_quad_spi@a0030000 {
compatible = "generic-uio";   -- Added 
};

};
};

};

 axi_quad_spi  node present in pl.dtsi file , based on that only you need to modify pl-custom.dtsi file

You can see the changes  after converting it from  dtbo to dtsi  file using “dtc -I dtb -O dts base.dtbo -o system.dtsi” command

 

Thanks & regards

Aravind

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aravindb
Moderator
Moderator
716 Views
Registered: ‎02-07-2018

Hi @James_Edgar 

You can modify pl device tree changes using pl-custom.dtsi file. so that after building it this changes will reflect in base.dtbo file.

Below is for your reference

/ {
fragment@2 {
target = <&amba_pl>;
overlay2: __overlay__ {

ethernet@a0100000 {
axistream-connected = <0x45>;
axistream-control-connected = <0x45>;

};
dma@a0010000 {
linux,phandle = <0x45>;
phandle = <0x45>;
};

axi_quad_spi@a0030000 {
compatible = "generic-uio";   -- Added 
};

};
};

};

 axi_quad_spi  node present in pl.dtsi file , based on that only you need to modify pl-custom.dtsi file

You can see the changes  after converting it from  dtbo to dtsi  file using “dtc -I dtb -O dts base.dtbo -o system.dtsi” command

 

Thanks & regards

Aravind

----------------------------------------------------------------------------------------------
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James_Edgar
Observer
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Registered: ‎08-24-2020

For anyone else missing the pl_mem sections after rebuild, attached is the file I added so they would be included with a new .xsa build.  (.txt added to file name so it will not be deleted on post)  Edited to replace file with 2020.1 version.

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fbalakirev
Contributor
Contributor
454 Views
Registered: ‎03-20-2014

@James_Edgar @aravindb do you happen to know how and where are starting addresses for each of the DACs and ADCs set? I would like to modify DDR buffer memory allocations among the channel and could not find it in pl_mem.c or in the pl-custom.dtsi that you have included.

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James_Edgar
Observer
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Registered: ‎08-24-2020
The absolute addresses for the DMA are set in Vivado in the Address editor which is there when the block diagram is open.  You would need to rebuild the whole project to change that.  Each of the pl_mem blocks in the file attached above indicates a size:
 
pl_mem_dac {
compatible = "xlnx,pl-mem";
xlnx,dac-device;
minor-number = <0x00>;
memory-region = <0xffffffff>;
dmas = <&dac_dma_block_axi_dma_0 0x00>;
dma-names = "dac";
size = <0x8000000>;
phandle = <0x61>;
};
I have not tried modifying those, but I assume if you did you could vary the sizes as well.  If you have a working project, you should try decompiling the associated dtbo file, changing those values, and recompiling it to test with what you have to verify that this works.  I have not seen another reference to the sizes, but since I have not tried it I am not certain that this is how the OS decides how big they are.
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fbalakirev
Contributor
Contributor
356 Views
Registered: ‎03-20-2014

@James_Edgar 

I checked that both DAC and ADC DMA modules assigned a single shared block of 4G PL DDR in Vivado's  zcu111 evaluation design. 

It appears that the memory is split between channels at the pl_mem driver level, according to what I see in the 2020.2 bsp sources

project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi

reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;
		plmem_pool0: pool0_mem_region {
			compatible = "shared-dma-pool";
			reg = <0x4 0x10000000 0x0 0x8000000>;
		};
		plmem_pool1: pool1_mem_region {
			compatible = "shared-dma-pool";
			reg = <0x4 0x18000000 0x0 0x8000000>;
		};

...
		plmem_pool14: pool14_mem_region {
			compatible = "shared-dma-pool";
			reg = <0x4 0x80000000 0x0 0x8000000>;
		};
		plmem_pool15: pool15_mem_region {
			compatible = "shared-dma-pool";
			reg = <0x4 0x88000000 0x0 0x8000000>;
		};
	};

 

 

project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi

 

	fragment@2 {
		target = <&amba>; 
	overlay2: __overlay__ {
	pl_mem_dac: pl_mem_dac {
		compatible = "xlnx,pl-mem";
		xlnx,dac-device;	
		minor-number = <0>;	
		memory-region = <&plmem_pool0>;
		dmas = <&dac_dma_block_axi_dma_0 0>;
		dma-names = "dac";
		size = <0x8000000>; 
	};
	pl_mem_dac1: pl_mem_dac1 {
		compatible = "xlnx,pl-mem";
		xlnx,dac-device;	
		minor-number = <1>;	
		memory-region = <&plmem_pool1>;
		size = <0x8000000>; 

...
	pl_mem_adc6: pl_mem_adc6 {
		compatible = "xlnx,pl-mem";
		xlnx,adc-device;	
		minor-number = <14>;	
		memory-region = <&plmem_pool14>;
		size = <0x8000000>; 
	};
	pl_mem_adc7: pl_mem_adc7 {
		compatible = "xlnx,pl-mem";
		xlnx,adc-device;
		minor-number = <15>;	
		memory-region = <&plmem_pool15>;
		size = <0x8000000>; 
	};

 

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