Incorrect colors with Android on ZC706

[chandan_e]

I am trying to run Android on a ZC702 and ZC706 using the HDMI port for the display.

I downloaded and built Android 4.2 for the ZC702 following the directions on iveia.com. I built the bitstream from scratch with a design based on the TRD 14.5.(http://www.wiki.xilinx.com/Zynq+Base+TRD+14.5) by removing all IP except the logiCVC-ML framebuffer IP from Xylon.. I built the design both under ISE 4.7 and Vivado 2013.4 and both bitstreams work just fine with Android.

I then rebuilt the design under Vivado 2013.4 for the ZC706 board. The kernel, FSBL, and u-boot were all rebuilt. Android runs, but the colors on the display are incorrect, mostly pinks and greens instead of the blue themed colors that I see on the ZC702. Playing with the devicetree settings for the ADV7511 chip on the board only changes the colors slightly. Has anyone seen similar behavior?

I'm using an evaluation version of the latest logiCVC-ML IP and have compiled its latest drivers into the kernel.

Thanks,

Chandan

[dahenk]

I've been using Vivado and the Test Pattern Generator IP-block on the ZC702 board.

The signals are passed through an AXI4-Stream to Video Out block and finally by HDMI to a screen.

I also only get pink/magenta and green colors on every pattern.

I have tried several different settings on the TPG and Video Out block.

Currently testing YCbCr422 on TPG and YUV4:2:2 on Video Out. Have tried RGB earlier but almost same results.

[dahenk]

Current design:

https://www.dropbox.com/s/cocozybgy89fvir/Screenshot%202014-01-22%2015.36.51.png

[xylonsupport · Accepted solution]

Hi chandan_e,

The connection between logiCVC and ADV7511 on ZC702 and ZC706 is different, you can see this from schematics (see attached images). For this reason you need to change the logiCVC generic to change its output:

- ZC702: 16 bit signal, logiCVC should be set to output YUV 4:2:2 (C_DISPLAY_COLOR_SPACE = 1)

- ZC706: 24 bit signal, logiCVC should be set to output RGB (C_DISPLAY_COLOR_SPACE = 0)

Once you have proper connection to ADV7511 chip, you need to initialize it differently for ZC702 and ZC706. The parameter you need to change is csc-enable in ADV7511 driver configuration. For ZC702 it is set to 1 (csc-enable = <1>;) and for ZC706 it should be set to 0 (csc-enable = <0>;).

Hopefully this helps!

Best regards,

XylonSupport

[chandan_e]

Thanks for the information. A couple more questions for the Xylon folks:

1. I will have to change the pixel data width in the logiCVC-ML to 24 instead of the original 16, right?
2. Do I have to change the depth of layer 0 to 24 as well? I is currently set to 16.

Chandan

[chandan_e]

Yes, that fixed it. The colors are correct now with Android. There was a bug in the kernel's drivers/i2c/media/adv7511.c which caused the csc-enable = <0> in the devicetree to be ignored, but after fixing it, everything is working. Thanks for your help.

Chandan

[dahenk]

How does your device tree look?

I noticed there is no "i2c@1" in my i2c switch in my device tree. Is that what initializes the ADV7511?

[chandan_e]

Yes, the i2c@1 section in my devicetree looks like this:

i2c@1 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <1>;
    hdmio@39 {
        compatible = "adv7511";
        reg = <0x39>;
        /* CE
        interrupts = <0 54 4>;
        */
        interrupts = <0 58 4>;

        interrupt-parent = <&gic>;
        dma-request = <&logicvc0>;
        edid-addr = <0x50>;
        video-input {
            input-id = <0>; /* CE RGB/YCbCr 4:4:4 */

            input-style = <0>; /* ignored when input-id == 0 */

            input-color-depth = <8>;

            bit-justification = <1>; /* ignored if input-id 0 */
            hsync-polarity = <0>;
            vsync-polarity = <0>;
            clock-delay = <3>;
        };
        video-output {
            hdmi-mode = <0>;
            output-format = <0>;
            output-color-space = <0>;
            up-conversion = <0>;

            csc-enable = <0>; /* CE no colorspace conversion */
            csc-scaling-factor = <2>; /* CE ignored */
            csc-coefficients { /* CE ignored */
                a1 = <0x0B37>;
                a2 = <0x0800>;
                a3 = <0x0000>;
                a4 = <0x1A86>;
                b1 = <0x1A49>;
                b2 = <0x0800>;
                b3 = <0x1D3F>;
                b4 = <0x0422>;
                c1 = <0x0000>;
                c2 = <0x0800>;
                c3 = <0x0E2D>;
                c4 = <0x1914>;
            };
        };
    };
};

The main changes are video-input/input-id and video-output/csc-enable. In addition, there is a section of code in the adv7511 driver in the kernel that has a bug that causes the csc-enable = <0> to be ignored. The fix (diff) to the file drivers/media/i2c/adv7511.c is below:

*** orig/adv7511.c	2014-02-05 16:43:19.873555298 -0800
--- adv7511.c	2014-02-07 18:24:10.296742777 -0800
*************** static void adv7511_set_ofdt_config(stru
*** 1436,1441 ****
--- 1436,1445 ----
  		/* AVI infoframe: Limited range RGB (16-235) */
  		adv7511_wr_and_or(sd, 0x57, 0xf3, 0x04);
  	}
+     else {
+ 		/* CE disable CSC */
+ 		adv7511_wr_and_or(sd, 0x18, 0x7f, 0x00);
+     }
  
  	/* AVI Info, Audio Info */
  	adv7511_wr_and_or(sd, 0x44, 0xe7, 0x10);

Also, don't forget what the Xylon folks said above about the 24 bit data from the logiCVC to the ADV7511.

Good luck!

[dahenk]

Thanks.

I'm using a AXI4-stream-to-Video-out block on a ZC702 though, so I'm pretty sure it should be 16-bit for me (YUV4:2:2 / YCbCr422).

I haven't been able to compile the kernel myself though because I'm a linux noob and I'm using windows 8 at the moment :S

been trying to make it work on a Virtual Machine running debian but there are always weirder errors for every problem i solve. I was just kinda hoping that the device tree fix would magically be enough to fix my color issues :P

[chandan_e]

dahenk,

I looked at the adv7511 hardware user's guide and there might be an issue with the timing constraints (set_output_delay) on the HDMI ports. In fact, Xilinx doesn't have any constraints in their TRD which is pretty bad. I have a ZC702 as well and I noticed that the colors were ghastly and changed with each synthesis/par run. I don't have the correct constraints, but I made some that were very tight. Even though trce tells me I'm failing timing, the colors come out correctly. Here are the constraints I used:

set_output_delay -clock [get_clocks video_clk_p] 2 [get_ports HDMI_O_clk]
set_output_delay -clock [get_clocks video_clk_p] 1 [get_ports {HDMI_O_data* HDMI_O_de HDMI_O_hsync HDMI_O_vsync}]

You will have to change the names of your signals appropriately.

[ra]

The TRD does include a 2 ns output delay on the HDMI interface (see system_top.xdc line 38).

A better solution here, though, is to add constraints to ensure that the output FFs for the video data and sideband control signals are packed into IOBs (including the video clock forwarding to the ADV7511). This negates the need for clock to out constraints on the video signals and eliminates the run-to-run variability.

[chandan_e]

I'm actually using Vivado. Would you be able to give me the exact constraints, assuming the signal names in my post above?

I looked at both http://www.wiki.xilinx.com/Zynq+PCIe+TRD+14.6 (ZC706) and http://www.wiki.xilinx.com/Zynq+Base+TRD+14.5 (ZC702) and neither of them has a system_top.xdc.

Furthermore, the ZC706 TRD doesn't even have the correct pin locations for all 24 of the ADV7511 pins (only 16 pins similar to the ZC702 are listed) which was part of the reason why I had so much trouble getting the colors right in the first place. The Xylon folks set me straight here.

[ckohn]

You say you use Vivado but you're pointing to PlanAhead/XPS based releases. The latest Vivado release for the Zynq Base TRD is here:

http://www.wiki.xilinx.com/Zynq+Base+TRD+2013.3

The 2013.4 update is yet to be published.

The top-level coinstraints file is located at hardware/vivado/constrs/system_top.xdc . Once you have created and opened the project you can simply view and modify the file from within Vivado.

While the ZC706 TRD does not use all 24 pins, it doesn't mean it's incorrect. The output format is set to YUV 4:2:2 which only requires 16 data pins. The ADV7511 is configured for this mode. Only if you use RGB you will have use all 24 data pins and configure the ADV7511 accordingly.

[chandan_e]

The reason I used planAhead initially was to ensure that I could reproduce the TRD. My goal was to use Vivado, but there was no Vivado version of the TRD when I started last year. I mimicked the ISE design in Vivado and while doing so, could not find the top level constraints in the TRD.

If I understand the ADV7511 correctly, the pins for YCbCr 4:2:2 are different from the pins that are connected on the ZC706. See which pins are used in the 4:2:2 and 4:4:4 modes in the ADV7511 Programming Guide in section 4.3 "Video Setup". Looking at the schematic of the ZC706, the pins are connected for 4:4:4 mode only.

Also, I did use the pin assignment from the zc706 TRD initially, but couldn't get the colors correct at all till Xylon pointed out the pin assignments in one of the posts above. Even then, the colors were a little bit off on some of the pixels till I added the timing constraints on the ADV7511 pins.

Maybe a lot of the confusion can be clarified by telling you what I was trying to do. My goal was to run Android on a ZC706 with some IP that we have. We had to use Vivado since our IP is written in SystemVerilog and ISE doesn't support it. Since iveia (Xilinx's Android provider) had Android only on a zc702, I  established a baseline by borrowing a zc702 and rebuilding their design in ISE (which turns out not to be their design at all but the zc702 TRD which uses the YCbCr colorspace) After I got this working, I rebuilt the same design again for the zc702, but in Vivado. This is where I ran into the first color problem (the same one dahenk ran into). Some builds were okay, others were not, but least the pin assignments were correct.

I then rebuilt the same design for the zc706 in Vivado and I just couldn't get the colors right till the pin assignments were changed and the colorspace was changed to RGB.

It was very frustrating because there were so many other issues (zc706 shipment was delayed by over 8 weeks, kernel issues, etc.) and the color was the least of my problems. Anyway, this whole discussion is moot since I have the design working to my satisfaction now. I was just giving dahenk some pointers since no one else seemed to be doing it.

[keshava]

Hi Chandan,

    In ZYNQ PCIe TRD -  FPGA video out is in 4:2:2 format not in 4:4:4 format. 

Please find the following comment in the top level UCF(z7_pcie_trd.ucf) for quick reference.   

     # ADV7511 video input mode YCbCr 4:2:2, separate syncs, 16 bpp (ID = 1 / style 3)

As XYLON SUPPORT team mentioned - in ZC706 24 pins are connected between FPGA and ADV7511 and we can configure logiCVC in RGB format to use 24 pins. But we want to maintain similarity between ZYNQ Base and ZYNQ PCIe TRD - hence we are only using 16 bits( YCbCr format).

Both logiCVC IP output format and ADV7511 input format are configured for 16bit YCbCr. This combination requires only 16 pin mappings. Hence you are only seeing constraints for 16 pins in the UCF. 

Pin order of this 16 pins need not to be same as HDMI chip data pin order. It should only match with the corresponding 8 bits of Y and Cb/Cr. 

In both ZYNQ Base and PCIe TRD the ADV7511 is configured for YCbCr  input format. Only change in the register setting due to pin map difference in both the TRDs would be justification bit ( 0x48[4:3] )

       =>  0x48[4:3]  = 1 for Base TRD       

       =>  0x48[4:3]  = 0 for PCIe  TRD

Corresponding video input format details can be found in Table: 18 &19  - YCbCr 4:2:2 Formats (24, 20, or 16 bits) Input Data Mapping of ADV7511 Programming Guide.

For better timing closure "Pack I/O Registers/Latches into IOBs" is set as TRUE in the MAP properties for both inputs and outputs flops of the design. 

Please refer MAP report for the following: 

Command Line : map -intstyle pa -w -pr b -ignore_keep_hierarchy

Please let me know if you need further clarifications.

-Keshava 

[ckohn]

The ADV7511 is very flexible when it comes to its pin configuration targeting different color formats and color bit widths. Please take a look at the various combinations in the ADV7511 Hardware User Guide or Programming Guide for more information. As Keshava said, we picked one valid configuration for YUV 4:2:2 color space. It is the same format as in the Base TRD but due to the different pin-out, the ADV7511 configuration is different as explained by Keshava.

The most likely reasons for colors being off are:

1. Color swap on the data line for example Y and U/V pins are swapped
2. ADV7511 is not configured to match the color mapping on the data line coming out of the FPGA
3. ADV7511 clock delay needs to be fine-tuned
4. Pin/output delay constraints to prevent skew (IOB packing)

We will check the constraints in the design and make sure this is adressed if it's missing.

I'm glad you got the design up and running and I'm sorry to hear about the frustrating experience. I hope these posts clarify some of the magic behind the ADV7511 / FPGA interface and prevent users from running into similar problems in the future.

[dahenk]

chandan_e

Thank you so much for taking your time to return to this post with some more answers.

I haven't tested your suggestion yet, but I did find a line in system_top.xdc in the newest TRD that ra mentioned that says:

# 2ns of output delay for HDMI output
set_output_delay -clock video_clk -min 2.000 [get_ports hdmio_data*]

Which looks like it does the same as your suggestion.

Currently trying to get a LogicVC to function, because I assumed the YUV422 output from AXI4-stream-to-video-out was wrong format (Maybe with this fix it would have worked?).

So far I've managed to save a .bmp image with correct colors on the SD card  using a VDMA. Trying to figure out how to now read data back to the logicvc block and then output on HDMI using butchered logicvc drivers from xapp1167.

[dahenk]

How do I find the name of the clock I'm supposed to put the delay on?

[ckohn]

Referring to the 2013.3 design, there are two components to it.

The first is a simple clock period constraint:

# Differential input clock from SI570 clock synthesizer on ZC702
# Constrained to 148.5MHz (1080p60 video resolution)
create_clock -period 6.734 -name video_clk [get_ports video_clk_p]

The second is an I/O delay constraint:

# 2ns of output delay for HDMI output
set_output_delay -clock video_clk -min 2.000 [get_ports hdmio_data*]

The hdmi output clock pin is driven by the si570 clock that we named video_clock in the first step. Hope this makes sense.

Now if you want to place the HDMI output flops into IOBs you can replace step 2 with something like this:

set_property IOB TRUE [get_cells -hierarchical YCbCr_4_2_2_gen.*_o_reg*]

Again this is referring to the 2013.3 design with the logiCVC configured for YUV 4:2:2 output mode. The flop names will most likely be different for RGB mode.

A simple way to find this out is to open the implemented design in Vivado, then highlight the hdmi out I/O ports and open in schematic view and backtrack the signals to the flops. If you highlight the flop in the schematic view and then switch to device view, you can see where on the FPGA the flop has been placed. 

[luciferkonn]

hi

I'm trying to do the same things with you, I want to konw how to rebuilt the  kernel, FSBL, and u-boot,can you teach me some.

[jg_spitfire]

Hi @xylonsupport why does the CSC should be 0 for a 4:4:4 input and 1 for a 4:2:2 input?

thanks

[xylonsupport]

Hi jg_spitfire,

Are you referring to ADV7511 chip? If yes, are you referring to chip's input?

Please give us more information.

Best regards,

Xylon Support

[jg_spitfire]

Hi @xylonsupport 

yes, I am using adv7511 with my ac701 board, I am talking about the input which is 4:4:4 for this board:

my confusion is because in this tutorial about adv7511 he enables CSC and makes a conversion from 4:2:2 (he is using a zc702 board) to RGB but I don´t understand why, so I saw your answer in this forum and I disabled the CSC but I still can not get a video signal in my monitor, but I am able to detect de HPD pin reading the ADV7511 0x42 register, he makes this config after dettect HPD signal:

// Power-up the Tx
	iic_write2(IicPs, Address, 0x41,0x10);


	// Fixed registers that must be set on power up
	iic_write2(IicPs, Address, 0x98, 0x03);
	iic_write2(IicPs, Address, 0x9A, 0xE0);
	iic_write2(IicPs, Address, 0x9C, 0x30);
	iic_write2(IicPs, Address, 0x9D, 0x61);
	iic_write2(IicPs, Address, 0xA2, 0xA4);
	iic_write2(IicPs, Address, 0xA3, 0xA4);
	iic_write2(IicPs, Address, 0xE0, 0xD0);
	iic_write2(IicPs, Address, 0xF9, 0x00);

	// Color Space Conversion
	iic_write2(IicPs, Address, 0x18, 0xE7); //CSC Enabled (YCbCr to RGB)

	// Set RGB in AVinfo Frame
	iic_write2(IicPs, Address, 0x55, 0x00);
	// Aspect Ration
	iic_write2(IicPs, Address, 0x56, 0x28);

	// HPD Control always high
	iic_write2(IicPs, Address, 0xD6, 0xC0);

	// DVI Mode, no HDCP
	iic_write2(IicPs, Address, 0xAF, 0x04);

	// Fixed I2C Address
	iic_write2(IicPs, Address, 0xF9, 0x00);

thanks

[xylonsupport]

Hi jg_spitfire,

First and foremost, we need to know do you use logiCVC in your design? Or any of our products?

Best regards,

Xylon Support

[jg_spitfire]

Hi @xylonsupport this is my block design

[xylonsupport]

Hi jg_spitfire

As you are not using any of our products, including video controller (logiCVC), we cannot provide you further support on this matter. You will need to contact company whose product you are using.

Best regards,

Xylon Support