UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor martind1983
Visitor
7,278 Views
Registered: ‎10-26-2014

Is 'petalinux-gen-zynq-boot' removed in the Petalinux SDK 2013.10?

Hello everybody

 

I have such a small strange issue. ;)

 

I use OS Ubuntu 14.04 LTS and Vvado 2015.2 for hw developing and petalinux-tools 2015.2 for whole embedded system solution

 

I downloaded "Avnet-Digilent-ZedBoard-v2015.2.1-final.bsp" package and built everything according to official petalinux manuals. Everything went fine I tried pre-built files also built files in this package and I could have boot all of them and run it on Zedboard

 

Then I created my own project <my_project> by means of "petalinux-create --type project --template zynq --name <name of my project> and fetched by command "petalinux-config --get-hw-description -p <my project folder>"  my hw solution from Vivado into project. I modified system config menu and build solution by command "petalinux-build" everything passed fine and I got "images" directory with all necessary files to boot system.

 

In turn I created BOOT.BIN file by command "petalinux-package --boot --fsbl zynq_fsbl.elf --fpga <my hw bitstream file> --u-boot", BOOT.BIN was created and I flashed BOOT.BIN with "image.ub" into boot partition of SD card

 

Problem is that system does not want to boot in contrast to system built from "Avnet-Digilent-ZedBoard-v2015.2.1-final.bsp" package.

 

Then I tried one trick. I took only "zynq_fsbl.elf" file from "Avnet-Digilent-ZedBoard-v2015.2.1-final.bsp" package and used it with generated bitstream and u-boot file from my project to create BOOT.BIN and such a created BOOT.BIN file already boots on my ZedBoard.

 

As you can see zynq_fsbl from Avnet 2015.2 package is a bit bigger. Is it possible that generated zynq_fsbl.elf file from my own project is somehow corrupted? I do not understand that because I do not get any errors before in building process related to fsbl file.

 

 

total 40312
drwxr-xr-x 2 root root     4096 Dec  7 18:49 ./
drwxr-xr-x 3 root root     4096 Dec  7 14:02 ../
-rwxr-xr-x 1 root root  7059024 Dec  7 15:29 image.elf*
-rw-r--r-- 1 root root  3488112 Dec  7 15:29 image.ub
-rw-r--r-- 1 root root  4784208 Dec  7 15:34 rootfs.jffs2
-rw-r--r-- 1 root root    14373 Dec  7 15:29 system.dtb
-rw-r--r-- 1 root root  1886549 Dec  7 15:29 System.map.linux
-rw-r--r-- 1 root root  4045683 Dec  6 12:04 Tutorial_design_wrapper.bit
-rwxr-xr-x 1 root root   296548 Dec  7 15:29 u-boot.bin*
-rwxr-xr-x 1 root root  1826898 Dec  7 15:29 u-boot.elf*
-rwxr-xr-x 1 root root   296548 Dec  7 15:29 u-boot-s.bin*
-rwxr-xr-x 1 root root  1826898 Dec  7 15:29 u-boot-s.elf*
-rwxr-xr-x 1 root root   852648 Dec  7 15:29 u-boot.srec*
-rwxr-xr-x 1 root root   852706 Dec  7 15:29 u-boot-s.srec*
-rwxr-xr-x 1 root root 10388709 Dec  7 15:29 vmlinux*
-rwxr-xr-x 1 root root  3488984 Dec  7 15:29 zImage*
-rwxr-xr-x 1 root root   288798 Dec  7 18:49 zynq_fsbl.elf*
martin@martin-HP:~/NOC_research/PetaLinux/tutorial_design/images/linux$ l ../../../Avnet-Digilent-ZedBoard-2015.2/images/linux/
total 67828
drwxrwxr-x 2 martin martin     4096 Dec  6 22:39 ./
drwxrwxr-x 3 martin martin     4096 Dec  6 15:15 ../
-rw-r--r-- 1 root   root    4446464 Dec  6 22:39 BOOT.BIN
-rw-rw-r-- 1 martin martin  4045671 Aug 17 21:27 download.bit
-rwxrwxr-x 1 martin martin 10491024 Dec  6 15:19 image.elf*
-rw-rw-r-- 1 martin martin  6924436 Dec  6 15:20 image.ub
-rw-rw-r-- 1 martin martin  7823872 Dec  6 15:19 rootfs.cpio
-rw-rw-r-- 1 martin martin  3466479 Dec  6 15:19 rootfs.cpio.gz
-rw-rw-r-- 1 martin martin    14548 Dec  6 15:19 system.dtb
-rw-rw-r-- 1 martin martin  1884839 Dec  6 15:20 System.map.linux
-rwxrwxr-x 1 martin martin   296640 Dec  6 15:19 u-boot.bin*
-rwxrwxr-x 1 martin martin  1842322 Dec  6 15:19 u-boot.elf*
-rwxrwxr-x 1 martin martin   296640 Dec  6 15:20 u-boot-s.bin*
-rwxrwxr-x 1 martin martin  1842322 Dec  6 15:20 u-boot-s.elf*
-rwxrwxr-x 1 martin martin   852916 Dec  6 15:19 u-boot.srec*
-rwxrwxr-x 1 martin martin   852974 Dec  6 15:20 u-boot-s.srec*
-rw-rw-r-- 1 martin martin  3466543 Dec  6 15:19 urootfs.cpio.gz
-rwxrwxr-x 1 martin martin 13818371 Dec  6 15:20 vmlinux*
-rwxrwxr-x 1 martin martin  6925136 Dec  6 15:20 zImage*
-rwxrwxr-x 1 martin martin   288946 Dec  6 15:19 zynq_fsbl.elf*

 

Thanks for your help

 

Br Martin :)

 

0 Kudos
4 Replies
Visitor martind1983
Visitor
7,276 Views
Registered: ‎10-26-2014

Re: Is 'petalinux-gen-zynq-boot' removed in the Petalinux SDK 2013.10?

I apologize for bad title probably automatic topic browser changed it when I typed title and I did not noticed it.
The name should be "BOOT.BIN does not want to boot (petalinux 2015.2)"
0 Kudos
Xilinx Employee
Xilinx Employee
7,274 Views
Registered: ‎09-10-2008

Re: Is 'petalinux-gen-zynq-boot' removed in the Petalinux SDK 2013.10?

It sounds like you might not have configured the h/w system correctly in Vivado as your FSBL is just doing what you told it to do (likely). Make sure earlyprintk is on in the kernel command line (likely is).

Thanks
John
0 Kudos
Visitor martind1983
Visitor
7,272 Views
Registered: ‎10-26-2014

Re: Is 'petalinux-gen-zynq-boot' removed in the Petalinux SDK 2013.10?

Hi linnj

Yes, earlyprintk is switched on by default. However, the problem is I can't see any kernel logs because. It does not boot at all. I do not even see blue LED done on Zedboard to switch on what probably means that PS was successfully configured. Board is completely depth with my generated zynq_fsbl.elf file. Is there way how to debug it or check some logs what can be wrong?
0 Kudos
Xilinx Employee
Xilinx Employee
7,269 Views
Registered: ‎09-10-2008

Re: Is 'petalinux-gen-zynq-boot' removed in the Petalinux SDK 2013.10?

If the UART is wrong in the Vivado system then you'll never get any output. Did you select the Zed Board in Vivado then leave the UART alone so that it should work? You need a baseline in Vivado then make changes from there.
0 Kudos