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Visitor kpr29806
Visitor
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Registered: ‎04-17-2018

Issue with AXI Quad SPI Slave

This concerns a ZC702 dev board running Linux.

I have two AXI QUAD SPI IP cores instantiated on the fabric. They are physically connected to one another through an FMC 105 debug breakout.

From Linux, writing data to the slave SPI's Data Transmit Register (DTR) will push that data onto its TX FIFO; no transaction will occur. Writing data to an enabled master's DTR will push that data onto its TX FIFO and cause the controller to issue a transaction (assert the slave-select line, run the clock, shift data out from the TX FIFO onto MOSI, shift data from MISO into the RX FIFO).

The following diagram describes some odd behavior that I've noticed when the slave SPI TX FIFO is loaded with more than one word at a time, and the master SPI then issues more than 1 transaction.

I hope it's clear enough. I have the slave SPI device at physical address 0x43C00000 and the master at 0x43C20000. When I load the slave SPI TX FIFO with more than one word of data and then use the master SPI to issue transactions, the first word is clocked out of the MISO line twice before the second word.

The compatible string for both SPI devices in pl.dtsi is compatible = "xlnx,xps-spi-2.00.a" -- I've scanned the device driver source for potential bugs but it doesn't look like there's any logic for dealing with the device in slave mode.

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AXI_QUAD_SPI_Slave_Issue.png
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Visitor kpr29806
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Registered: ‎04-17-2018

Re: Issue with AXI Quad SPI Slave

After doing a little more research, it seems like I'm having the same problem as tim99 in this forum post (seeing a repeated first byte).

However, a look at the oscilloscope shows that I'm "dynamically" asserting the SS line, i.e. it goes low for the duration of the transaction and goes high again immediately after.

dynamic_ss.PNGSS driven low for duration of transaction only

 

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Visitor kpr29806
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Registered: ‎04-17-2018

Re: Issue with AXI Quad SPI Slave

Another update: pg 63 of the IP programmer's guide (PG153), at the end of the Clocking section, states that "It is required that all SSn signals be routed between devices internally to the FPGA."

I updated my design so that the Master's SS[0] line and the Slave's SPISEL line are not external pins, removed their physical constraints from the XDC, and tied them together in the block diagram wrapper (internal to the FPGA).

Unfortunately the same behavior remains (repeated first byte). Here are the commands as issued in Linux: Notice that I insert 0xdead and 0xbeef into the slave FIFO, but the first two transactions from the Master both return 0xdead and 0xbeef only arrives on the 3rd transaction!

root@xilinx-zc702-2017_4:~# devmem 0x43C00068 16 0xdead
root@xilinx-zc702-2017_4:~# devmem 0x43C00068 16 0xbeef
root@xilinx-zc702-2017_4:~# devmem 0x43C20068 16 0x1
root@xilinx-zc702-2017_4:~# devmem 0x43C20068 16 0x5
root@xilinx-zc702-2017_4:~# devmem 0x43C20068 16 0x5
root@xilinx-zc702-2017_4:~# devmem 0x43C0006C
0x00000001
root@xilinx-zc702-2017_4:~# devmem 0x43C0006C
0x00000005
root@xilinx-zc702-2017_4:~# devmem 0x43C0006C
0x00000005
root@xilinx-zc702-2017_4:~# devmem 0x43C0006C
Bus error
root@xilinx-zc702-2017_4:~# devmem 0x43C2006C
0x0000DEAD
root@xilinx-zc702-2017_4:~# devmem 0x43C2006C
0x0000DEAD
root@xilinx-zc702-2017_4:~# devmem 0x43C2006C
0x0000BEEF
root@xilinx-zc702-2017_4:~# devmem 0x43C2006C
Bus error
root@xilinx-zc702-2017_4:~# 

Here are the core's Control and Status registers (at offset 0x60 and 0x64 respectively)

root@xilinx-zc702-2017_4:~# devmem 0x43C20064
0x00000025
root@xilinx-zc702-2017_4:~# devmem 0x43C20060
0x00000006
root@xilinx-zc702-2017_4:~# devmem 0x43C00064
0x00000025
root@xilinx-zc702-2017_4:~# devmem 0x43C00060
0x00000002
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