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Scholar vanmierlo
Scholar
2,335 Views
Registered: ‎06-10-2008

Linux FIFO to PL

Hi all,

 

I'm kinda at a loss. I want to create a solution where I can write data to some device from Linux on the Zynq PS and have the data come out a FIFO on the PL side. Later on I will also need the reverse. But where to start?

 

I've looked into AXI and it seems it cannot bridge to the FIFO interface kind I'm used to which is the BRAM based Core Generator FIFO. It appears I can only create a FIFO with both AXI or both native. I don't understand why, because my question seems obvious to me. Should I bite the bullet and learn all about AXI interfacing just to be able to get some data out of a fifo?

 

Then I also don't have clue where to start to create a linux device driver for an AXI FIFO. I saw something called xstreamer and xpacket_fifo but I can find no info on them. Maybe I'm just looking in the wrong place, but Google certainly does not seem to be my friend today.

 

Please help,

Maarten

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Scholar austin
Scholar
2,331 Views
Registered: ‎02-27-2008

Re: Linux FIFO to PL

m,

 

The AXI4 interface pioneered by Xilinx and ARM for Zynq specifically has a streaming mode (uses the PL FIFO/BRAM0.

 

Look at the video demo, as video is the use case for this.

 

Vivado HLS has pragmas to direct the use of the streaming interface, so all of that is generated to support your c code function.

 

That is probably the fastest way to get to a working system, with the least amount of pain.

 

 

http://www.google.com/url?sa=t&rct=j&q=xilinx%20axi4%20fifo&source=web&cd=3&cad=rja&ved=0CDoQFjAC&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fip_documentation%2Faxi_fifo_mm_s%2Fv3_00_b%2Fpg080-axi-fifo-mm-s.pdf&ei=icfmUejnOsm2igKdrIGA...

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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