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Visitor
Visitor
3,180 Views
Registered: ‎09-02-2008

Linux not booting on ml507 when SRAM is used instead of SDRAM

Hi,

 

I am trying to use linux-2.6.30 on ML507 board, with SRAM.

 

I could get Linux running on design (created using BSB) with 16Mb of SDRAM.

 

But when i created another design  (created using BSB)  with 16Mb of SRAM, Linux is not booting , no o/p in the console..

 

There is no change in these designs other than the memory.

 

Can someone  tell me , why is this..? will linux boot only with SDRAM? or Am i missing something..?

 

 

Bellow is the device tree for the desighn with SRAM. 

 

 

 

Thanks,

Sumesh. 

 

/dts-v1/;

/ {

#address-cells = <1>;

#size-cells = <1>;

compatible = "xlnx,virtex440", "xlnx,virtex";

dcr-parent = <&ppc440_0>;

model = "testing";

SRAM: memory@0 {

device_type = "memory";

reg = < 0x0 0x1000000 >;

} ;

aliases {

serial0 = &RS232_Uart_1;

} ;

chosen {

bootargs = "console=ttyS0 root=/dev/ram";

} ;

cpus {

#address-cells = <1>;

#cpus = <0x1>;

#size-cells = <0>;

ppc440_0: cpu@0 {

#address-cells = <1>;

#size-cells = <1>;

clock-frequency = <125000000>;

compatible = "PowerPC,440", "ibm,ppc440";

d-cache-line-size = <0x20>;

d-cache-size = <0x8000>;

dcr-access-method = "native";

dcr-controller ;

device_type = "cpu";

i-cache-line-size = <0x20>;

i-cache-size = <0x8000>;

model = "PowerPC,440";

reg = <0>;

timebase-frequency = <125000000>;

xlnx,apu-control = <0x2000>;

xlnx,apu-udi-0 = <0x0>;

xlnx,apu-udi-1 = <0x0>;

xlnx,apu-udi-10 = <0x0>;

xlnx,apu-udi-11 = <0x0>;

xlnx,apu-udi-12 = <0x0>;

xlnx,apu-udi-13 = <0x0>;

xlnx,apu-udi-14 = <0x0>;

xlnx,apu-udi-15 = <0x0>;

xlnx,apu-udi-2 = <0x0>;

xlnx,apu-udi-3 = <0x0>;

xlnx,apu-udi-4 = <0x0>;

xlnx,apu-udi-5 = <0x0>;

xlnx,apu-udi-6 = <0x0>;

xlnx,apu-udi-7 = <0x0>;

xlnx,apu-udi-8 = <0x0>;

xlnx,apu-udi-9 = <0x0>;

xlnx,dcr-autolock-enable = <0x1>;

xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;

xlnx,dcu-rd-noncache-plb-prio = <0x0>;

xlnx,dcu-rd-touch-plb-prio = <0x0>;

xlnx,dcu-rd-urgent-plb-prio = <0x0>;

xlnx,dcu-wr-flush-plb-prio = <0x0>;

xlnx,dcu-wr-store-plb-prio = <0x0>;

xlnx,dcu-wr-urgent-plb-prio = <0x0>;

xlnx,dma0-control = <0x0>;

xlnx,dma0-plb-prio = <0x0>;

xlnx,dma0-rxchannelctrl = <0x1010000>;

xlnx,dma0-rxirqtimer = <0x3ff>;

xlnx,dma0-txchannelctrl = <0x1010000>;

xlnx,dma0-txirqtimer = <0x3ff>;

xlnx,dma1-control = <0x0>;

xlnx,dma1-plb-prio = <0x0>;

xlnx,dma1-rxchannelctrl = <0x1010000>;

xlnx,dma1-rxirqtimer = <0x3ff>;

xlnx,dma1-txchannelctrl = <0x1010000>;

xlnx,dma1-txirqtimer = <0x3ff>;

xlnx,dma2-control = <0x0>;

xlnx,dma2-plb-prio = <0x0>;

xlnx,dma2-rxchannelctrl = <0x1010000>;

xlnx,dma2-rxirqtimer = <0x3ff>;

xlnx,dma2-txchannelctrl = <0x1010000>;

xlnx,dma2-txirqtimer = <0x3ff>;

xlnx,dma3-control = <0x0>;

xlnx,dma3-plb-prio = <0x0>;

xlnx,dma3-rxchannelctrl = <0x1010000>;

xlnx,dma3-rxirqtimer = <0x3ff>;

xlnx,dma3-txchannelctrl = <0x1010000>;

xlnx,dma3-txirqtimer = <0x3ff>;

xlnx,endian-reset = <0x0>;

xlnx,generate-plb-timespecs = <0x1>;

xlnx,icu-rd-fetch-plb-prio = <0x0>;

xlnx,icu-rd-spec-plb-prio = <0x0>;

xlnx,icu-rd-touch-plb-prio = <0x0>;

xlnx,interconnect-imask = <0xffffffff>;

xlnx,mplb-allow-lock-xfer = <0x1>;

xlnx,mplb-arb-mode = <0x0>;

xlnx,mplb-awidth = <0x20>;

xlnx,mplb-counter = <0x500>;

xlnx,mplb-dwidth = <0x80>;

xlnx,mplb-max-burst = <0x8>;

xlnx,mplb-native-dwidth = <0x80>;

xlnx,mplb-p2p = <0x0>;

xlnx,mplb-prio-dcur = <0x2>;

xlnx,mplb-prio-dcuw = <0x3>;

xlnx,mplb-prio-icu = <0x4>;

xlnx,mplb-prio-splb0 = <0x1>;

xlnx,mplb-prio-splb1 = <0x0>;

xlnx,mplb-read-pipe-enable = <0x1>;

xlnx,mplb-sync-tattribute = <0x0>;

xlnx,mplb-wdog-enable = <0x1>;

xlnx,mplb-write-pipe-enable = <0x1>;

xlnx,mplb-write-post-enable = <0x1>;

xlnx,num-dma = <0x0>;

xlnx,pir = <0xf>;

xlnx,ppc440mc-addr-base = <0xffffffff>;

xlnx,ppc440mc-addr-high = <0x0>;

xlnx,ppc440mc-arb-mode = <0x0>;

xlnx,ppc440mc-bank-conflict-mask = <0x0>;

xlnx,ppc440mc-control = <0x8f>;

xlnx,ppc440mc-max-burst = <0x8>;

xlnx,ppc440mc-prio-dcur = <0x2>;

xlnx,ppc440mc-prio-dcuw = <0x3>;

xlnx,ppc440mc-prio-icu = <0x4>;

xlnx,ppc440mc-prio-splb0 = <0x1>;

xlnx,ppc440mc-prio-splb1 = <0x0>;

xlnx,ppc440mc-row-conflict-mask = <0x0>;

xlnx,ppcdm-asyncmode = <0x0>;

xlnx,ppcds-asyncmode = <0x0>;

xlnx,user-reset = <0x0>;

} ;

} ;

plb_v46_0: plb@0 {

#address-cells = <1>;

#size-cells = <1>;

compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";

ranges ;

RS232_Uart_1: serial@83e00000 {

clock-frequency = <125000000>;

compatible = "xlnx,xps-uart16550-2.00.b", "xlnx,xps-uart16550-2.00.a", "ns16550";

current-speed = <9600>;

device_type = "serial";

interrupt-parent = <&xps_intc_0>;

interrupts = < 0 2 >;

reg = < 0x83e00000 0x10000 >;

reg-offset = <0x1003>;

reg-shift = <2>;

xlnx,family = "virtex5";

xlnx,has-external-rclk = <0x0>;

xlnx,has-external-xin = <0x0>;

xlnx,is-a-16550 = <0x1>;

} ;

xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {

compatible = "xlnx,xps-bram-if-cntlr-1.00.a";

reg = < 0xffff0000 0x10000 >;

xlnx,family = "virtex5";

} ;

xps_intc_0: interrupt-controller@81800000 {

#interrupt-cells = <0x2>;

compatible = "xlnx,xps-intc-1.00.a";

interrupt-controller ;

reg = < 0x81800000 0x10000 >;

xlnx,num-intr-inputs = <0x1>;

} ;

} ;

}  ;

 

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1 Reply
Xilinx Employee
Xilinx Employee
3,164 Views
Registered: ‎09-10-2008

If the device tree is the same other than the name of the memory, then I would question if your SRAM is solid.

 

Have you done good testing of your SRAM in a stand alone application before trying to boot Linux?

 

We have seen stand alone apps test memory and it be fine and Linux will still find memory issues.  Linux does tend to stress things.

 

I see no reason that the kernel will care or know the difference if the SRAM at the same address (0).  But I can't say I've done it before.

 

-- John

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