05-07-2021 01:58 AM
I am running vivado/petalinux 2018.2 on our Zynq7000 custom board. Our design consists on multiple AXI UART 16550 blocks that keep changing based on different systems. I want to have a design where I can keep the core design (with SD,emmc, gem0 etc) that does not change within the dts file and to have the additional option to load the variable 8250 driver for the AXI UART 16550 blocks at runtime. One option could be to use a seperate dtb file and store it in flash but I would like to have a system where the I can just load the modules at runtime without touching the dtb/image.ub stored in the flash. Is there a way that I can pass the AXI UART 16550 reg address and interrupt to the 8250 driver instance during runtime? I had a similar setup working under QNX. I would like to do the same thing using petalinux. Is there any way to accomplish this?
05-21-2021 02:40 AM
You can have a register in the UART IP and read this during driver init, and call the respective module. This is how the PHY driver framework handles multiple phy drivers.
05-21-2021 05:43 AM
Hi @stephenm ,
Thanks for the reply. I did not understand. It is clear which driver should be loaded and the IP is also the standard IP from xilinx (AXI UART 16550). The only problem is that there are n number of UART IPs and I have to find a way to load drivers for them after the kernel has booted.