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mathew.e
Visitor
Visitor
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Registered: ‎02-02-2011

Low Ethernet bandwidth

We are using Virtex 5(xc5vfx100t) in our custom board. We ported Linux(2.6.35) over PPC440 on the above FPGA.

The Linux is coming up properly every time. But sometimes the Ethernet bandwidth we are getting is very less(2 to 3 Mbps).

Sometimes the bandwidth is proper.  We are using iperf for measuring the bandwidth.

The dts file and the xparameters.h file are attached.

 

 

 

/*
 * Device Tree Generator version: 1.3
 *
 * (C) Copyright 2007-2008 Xilinx, Inc.
 * (C) Copyright 2007-2009 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * CAUTION: This file is automatically generated by libgen.
 * Version: Xilinx EDK 12.1 EDK_MS1.53d
 *
 * XPS project directory: RTIO_sig_gen_working
 */
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,virtex440", "xlnx,virtex";
dcr-parent = <&ppc440_0>;
model = "testing";
DDR2_SDRAM: memory@0 {
device_type = "memory";
reg = < 0x0 0x4000000 >;
} ;
aliases {
ethernet0 = &Hard_Ethernet_MAC;
serial0 = &RS232_Uart_1;
} ;
chosen {
bootargs = "console=ttyUL0 ip=172.16.10.100 root=/dev/ram rw ramdisk_size=16000 mtdparts=86000000.flash:6M(bits),9M(zImage),1M(loader)";
linux,stdout-path = "/plb@0/serial@84000000";
} ;
cpus {
#address-cells = <1>;
#cpus = <0x1>;
#size-cells = <0>;
ppc440_0: cpu@0 {
#address-cells = <1>;
#size-cells = <1>;
clock-frequency = <125000000>;
compatible = "PowerPC,440", "ibm,ppc440";
d-cache-line-size = <0x20>;
d-cache-size = <0x8000>;
dcr-access-method = "native";
dcr-controller ;
device_type = "cpu";
i-cache-line-size = <0x20>;
i-cache-size = <0x8000>;
model = "PowerPC,440";
reg = <0>;
timebase-frequency = <125000000>;
xlnx,apu-control = <0x2000>;
xlnx,apu-udi-0 = <0x0>;
xlnx,apu-udi-1 = <0x0>;
xlnx,apu-udi-10 = <0x0>;
xlnx,apu-udi-11 = <0x0>;
xlnx,apu-udi-12 = <0x0>;
xlnx,apu-udi-13 = <0x0>;
xlnx,apu-udi-14 = <0x0>;
xlnx,apu-udi-15 = <0x0>;
xlnx,apu-udi-2 = <0x0>;
xlnx,apu-udi-3 = <0x0>;
xlnx,apu-udi-4 = <0x0>;
xlnx,apu-udi-5 = <0x0>;
xlnx,apu-udi-6 = <0x0>;
xlnx,apu-udi-7 = <0x0>;
xlnx,apu-udi-8 = <0x0>;
xlnx,apu-udi-9 = <0x0>;
xlnx,dcr-autolock-enable = <0x1>;
xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
xlnx,dcu-rd-noncache-plb-prio = <0x0>;
xlnx,dcu-rd-touch-plb-prio = <0x0>;
xlnx,dcu-rd-urgent-plb-prio = <0x0>;
xlnx,dcu-wr-flush-plb-prio = <0x0>;
xlnx,dcu-wr-store-plb-prio = <0x0>;
xlnx,dcu-wr-urgent-plb-prio = <0x0>;
xlnx,dma0-control = <0x0>;
xlnx,dma0-plb-prio = <0x0>;
xlnx,dma0-rxchannelctrl = <0x1010000>;
xlnx,dma0-rxirqtimer = <0x3ff>;
xlnx,dma0-txchannelctrl = <0x1010000>;
xlnx,dma0-txirqtimer = <0x3ff>;
xlnx,dma1-control = <0x0>;
xlnx,dma1-plb-prio = <0x0>;
xlnx,dma1-rxchannelctrl = <0x1010000>;
xlnx,dma1-rxirqtimer = <0x3ff>;
xlnx,dma1-txchannelctrl = <0x1010000>;
xlnx,dma1-txirqtimer = <0x3ff>;
xlnx,dma2-control = <0x0>;
xlnx,dma2-plb-prio = <0x0>;
xlnx,dma2-rxchannelctrl = <0x1010000>;
xlnx,dma2-rxirqtimer = <0x3ff>;
xlnx,dma2-txchannelctrl = <0x1010000>;
xlnx,dma2-txirqtimer = <0x3ff>;
xlnx,dma3-control = <0x0>;
xlnx,dma3-plb-prio = <0x0>;
xlnx,dma3-rxchannelctrl = <0x1010000>;
xlnx,dma3-rxirqtimer = <0x3ff>;
xlnx,dma3-txchannelctrl = <0x1010000>;
xlnx,dma3-txirqtimer = <0x3ff>;
xlnx,endian-reset = <0x0>;
xlnx,generate-plb-timespecs = <0x1>;
xlnx,icu-rd-fetch-plb-prio = <0x0>;
xlnx,icu-rd-spec-plb-prio = <0x0>;
xlnx,icu-rd-touch-plb-prio = <0x0>;
xlnx,interconnect-imask = <0xffffffff>;
xlnx,mplb-allow-lock-xfer = <0x1>;
xlnx,mplb-arb-mode = <0x0>;
xlnx,mplb-awidth = <0x20>;
xlnx,mplb-counter = <0x500>;
xlnx,mplb-dwidth = <0x80>;
xlnx,mplb-max-burst = <0x8>;
xlnx,mplb-native-dwidth = <0x80>;
xlnx,mplb-p2p = <0x0>;
xlnx,mplb-prio-dcur = <0x2>;
xlnx,mplb-prio-dcuw = <0x3>;
xlnx,mplb-prio-icu = <0x4>;
xlnx,mplb-prio-splb0 = <0x1>;
xlnx,mplb-prio-splb1 = <0x0>;
xlnx,mplb-read-pipe-enable = <0x1>;
xlnx,mplb-sync-tattribute = <0x0>;
xlnx,mplb-wdog-enable = <0x1>;
xlnx,mplb-write-pipe-enable = <0x1>;
xlnx,mplb-write-post-enable = <0x1>;
xlnx,num-dma = <0x1>;
xlnx,pir = <0xf>;
xlnx,ppc440mc-addr-base = <0x0>;
xlnx,ppc440mc-addr-high = <0x3ffffff>;
xlnx,ppc440mc-arb-mode = <0x0>;
xlnx,ppc440mc-bank-conflict-mask = <0x0>;
xlnx,ppc440mc-control = <0x8060008f>;
xlnx,ppc440mc-max-burst = <0x8>;
xlnx,ppc440mc-prio-dcur = <0x2>;
xlnx,ppc440mc-prio-dcuw = <0x3>;
xlnx,ppc440mc-prio-icu = <0x4>;
xlnx,ppc440mc-prio-splb0 = <0x1>;
xlnx,ppc440mc-prio-splb1 = <0x0>;
xlnx,ppc440mc-row-conflict-mask = <0x0>;
xlnx,ppcdm-asyncmode = <0x0>;
xlnx,ppcds-asyncmode = <0x0>;
xlnx,user-reset = <0x0>;
DMA0: sdma@80 {
compatible = "xlnx,ll-dma-1.00.a";
dcr-reg = < 0x80 0x11 >;
interrupt-parent = <&xps_intc_0>;
interrupts = < 3 2 4 2 >;
} ;
} ;
} ;
plb_v46_0: plb@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,plb-v46-1.04.a", "xlnx,plb-v46-1.00.a", "simple-bus";
ranges ;
FLASH: flash@86000000 {
bank-width = <2>;
compatible = "xlnx,xps-mch-emc-3.01.a", "cfi-flash";
reg = < 0x86000000 0x1000000 >;
xlnx,family = "virtex5";
xlnx,include-datawidth-matching-0 = <0x1>;
xlnx,include-datawidth-matching-1 = <0x0>;
xlnx,include-datawidth-matching-2 = <0x0>;
xlnx,include-datawidth-matching-3 = <0x0>;
xlnx,include-negedge-ioregs = <0x0>;
xlnx,include-plb-ipif = <0x1>;
xlnx,include-wrbuf = <0x1>;
xlnx,max-mem-width = <0x10>;
xlnx,mch-native-dwidth = <0x20>;
xlnx,mch-splb-awidth = <0x20>;
xlnx,mch-splb-clk-period-ps = <0x1f40>;
xlnx,mch0-accessbuf-depth = <0x10>;
xlnx,mch0-protocol = <0x0>;
xlnx,mch0-rddatabuf-depth = <0x10>;
xlnx,mch1-accessbuf-depth = <0x10>;
xlnx,mch1-protocol = <0x0>;
xlnx,mch1-rddatabuf-depth = <0x10>;
xlnx,mch2-accessbuf-depth = <0x10>;
xlnx,mch2-protocol = <0x0>;
xlnx,mch2-rddatabuf-depth = <0x10>;
xlnx,mch3-accessbuf-depth = <0x10>;
xlnx,mch3-protocol = <0x0>;
xlnx,mch3-rddatabuf-depth = <0x10>;
xlnx,mem0-width = <0x10>;
xlnx,mem1-width = <0x20>;
xlnx,mem2-width = <0x20>;
xlnx,mem3-width = <0x20>;
xlnx,num-banks-mem = <0x1>;
xlnx,num-channels = <0x0>;
xlnx,pagemode-flash-0 = <0x0>;
xlnx,pagemode-flash-1 = <0x0>;
xlnx,pagemode-flash-2 = <0x0>;
xlnx,pagemode-flash-3 = <0x0>;
xlnx,priority-mode = <0x0>;
xlnx,synch-mem-0 = <0x0>;
xlnx,synch-mem-1 = <0x0>;
xlnx,synch-mem-2 = <0x0>;
xlnx,synch-mem-3 = <0x0>;
xlnx,synch-pipedelay-0 = <0x2>;
xlnx,synch-pipedelay-1 = <0x2>;
xlnx,synch-pipedelay-2 = <0x2>;
xlnx,synch-pipedelay-3 = <0x2>;
xlnx,tavdv-ps-mem-0 = <0x1adb0>;
xlnx,tavdv-ps-mem-1 = <0x3a98>;
xlnx,tavdv-ps-mem-2 = <0x3a98>;
xlnx,tavdv-ps-mem-3 = <0x3a98>;
xlnx,tcedv-ps-mem-0 = <0x1adb0>;
xlnx,tcedv-ps-mem-1 = <0x3a98>;
xlnx,tcedv-ps-mem-2 = <0x3a98>;
xlnx,tcedv-ps-mem-3 = <0x3a98>;
xlnx,thzce-ps-mem-0 = <0x88b8>;
xlnx,thzce-ps-mem-1 = <0x1b58>;
xlnx,thzce-ps-mem-2 = <0x1b58>;
xlnx,thzce-ps-mem-3 = <0x1b58>;
xlnx,thzoe-ps-mem-0 = <0x1b58>;
xlnx,thzoe-ps-mem-1 = <0x1b58>;
xlnx,thzoe-ps-mem-2 = <0x1b58>;
xlnx,thzoe-ps-mem-3 = <0x1b58>;
xlnx,tlzwe-ps-mem-0 = <0x88b8>;
xlnx,tlzwe-ps-mem-1 = <0x0>;
xlnx,tlzwe-ps-mem-2 = <0x0>;
xlnx,tlzwe-ps-mem-3 = <0x0>;
xlnx,tpacc-ps-flash-0 = <0x61a8>;
xlnx,tpacc-ps-flash-1 = <0x61a8>;
xlnx,tpacc-ps-flash-2 = <0x61a8>;
xlnx,tpacc-ps-flash-3 = <0x61a8>;
xlnx,twc-ps-mem-0 = <0x2af8>;
xlnx,twc-ps-mem-1 = <0x3a98>;
xlnx,twc-ps-mem-2 = <0x3a98>;
xlnx,twc-ps-mem-3 = <0x3a98>;
xlnx,twp-ps-mem-0 = <0x11170>;
xlnx,twp-ps-mem-1 = <0x2ee0>;
xlnx,twp-ps-mem-2 = <0x2ee0>;
xlnx,twp-ps-mem-3 = <0x2ee0>;
xlnx,xcl0-linesize = <0x4>;
xlnx,xcl0-writexfer = <0x1>;
xlnx,xcl1-linesize = <0x4>;
xlnx,xcl1-writexfer = <0x1>;
xlnx,xcl2-linesize = <0x4>;
xlnx,xcl2-writexfer = <0x1>;
xlnx,xcl3-linesize = <0x4>;
xlnx,xcl3-writexfer = <0x1>;
} ;
Generic_External_Memory: flash@10000000 {
bank-width = <4>;
compatible = "xlnx,xps-mch-emc-3.01.a", "cfi-flash";
reg = < 0x10000000 0x4000000 >;
xlnx,family = "virtex5";
xlnx,include-datawidth-matching-0 = <0x1>;
xlnx,include-datawidth-matching-1 = <0x0>;
xlnx,include-datawidth-matching-2 = <0x0>;
xlnx,include-datawidth-matching-3 = <0x0>;
xlnx,include-negedge-ioregs = <0x0>;
xlnx,include-plb-ipif = <0x1>;
xlnx,include-wrbuf = <0x1>;
xlnx,max-mem-width = <0x20>;
xlnx,mch-native-dwidth = <0x20>;
xlnx,mch-splb-awidth = <0x20>;
xlnx,mch-splb-clk-period-ps = <0x1f40>;
xlnx,mch0-accessbuf-depth = <0x10>;
xlnx,mch0-protocol = <0x0>;
xlnx,mch0-rddatabuf-depth = <0x10>;
xlnx,mch1-accessbuf-depth = <0x10>;
xlnx,mch1-protocol = <0x0>;
xlnx,mch1-rddatabuf-depth = <0x10>;
xlnx,mch2-accessbuf-depth = <0x10>;
xlnx,mch2-protocol = <0x0>;
xlnx,mch2-rddatabuf-depth = <0x10>;
xlnx,mch3-accessbuf-depth = <0x10>;
xlnx,mch3-protocol = <0x0>;
xlnx,mch3-rddatabuf-depth = <0x10>;
xlnx,mem0-width = <0x20>;
xlnx,mem1-width = <0x20>;
xlnx,mem2-width = <0x20>;
xlnx,mem3-width = <0x20>;
xlnx,num-banks-mem = <0x1>;
xlnx,num-channels = <0x0>;
xlnx,pagemode-flash-0 = <0x0>;
xlnx,pagemode-flash-1 = <0x0>;
xlnx,pagemode-flash-2 = <0x0>;
xlnx,pagemode-flash-3 = <0x0>;
xlnx,priority-mode = <0x0>;
xlnx,synch-mem-0 = <0x0>;
xlnx,synch-mem-1 = <0x0>;
xlnx,synch-mem-2 = <0x0>;
xlnx,synch-mem-3 = <0x0>;
xlnx,synch-pipedelay-0 = <0x2>;
xlnx,synch-pipedelay-1 = <0x2>;
xlnx,synch-pipedelay-2 = <0x2>;
xlnx,synch-pipedelay-3 = <0x2>;
xlnx,tavdv-ps-mem-0 = <0x1d4c0>;
xlnx,tavdv-ps-mem-1 = <0x3a98>;
xlnx,tavdv-ps-mem-2 = <0x3a98>;
xlnx,tavdv-ps-mem-3 = <0x3a98>;
xlnx,tcedv-ps-mem-0 = <0x1d4c0>;
xlnx,tcedv-ps-mem-1 = <0x3a98>;
xlnx,tcedv-ps-mem-2 = <0x3a98>;
xlnx,tcedv-ps-mem-3 = <0x3a98>;
xlnx,thzce-ps-mem-0 = <0x4e20>;
xlnx,thzce-ps-mem-1 = <0x1b58>;
xlnx,thzce-ps-mem-2 = <0x1b58>;
xlnx,thzce-ps-mem-3 = <0x1b58>;
xlnx,thzoe-ps-mem-0 = <0x4e20>;
xlnx,thzoe-ps-mem-1 = <0x1b58>;
xlnx,thzoe-ps-mem-2 = <0x1b58>;
xlnx,thzoe-ps-mem-3 = <0x1b58>;
xlnx,tlzwe-ps-mem-0 = <0x0>;
xlnx,tlzwe-ps-mem-1 = <0x0>;
xlnx,tlzwe-ps-mem-2 = <0x0>;
xlnx,tlzwe-ps-mem-3 = <0x0>;
xlnx,tpacc-ps-flash-0 = <0x61a8>;
xlnx,tpacc-ps-flash-1 = <0x61a8>;
xlnx,tpacc-ps-flash-2 = <0x61a8>;
xlnx,tpacc-ps-flash-3 = <0x61a8>;
xlnx,twc-ps-mem-0 = <0x1d4c0>;
xlnx,twc-ps-mem-1 = <0x3a98>;
xlnx,twc-ps-mem-2 = <0x3a98>;
xlnx,twc-ps-mem-3 = <0x3a98>;
xlnx,twp-ps-mem-0 = <0x88b8>;
xlnx,twp-ps-mem-1 = <0x2ee0>;
xlnx,twp-ps-mem-2 = <0x2ee0>;
xlnx,twp-ps-mem-3 = <0x2ee0>;
xlnx,xcl0-linesize = <0x4>;
xlnx,xcl0-writexfer = <0x1>;
xlnx,xcl1-linesize = <0x4>;
xlnx,xcl1-writexfer = <0x1>;
xlnx,xcl2-linesize = <0x4>;
xlnx,xcl2-writexfer = <0x1>;
xlnx,xcl3-linesize = <0x4>;
xlnx,xcl3-writexfer = <0x1>;
} ;
Hard_Ethernet_MAC: xps-ll-temac@81880000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,compound";
ethernet@81880000 {
compatible = "xlnx,xps-ll-temac-2.03.a", "xlnx,xps-ll-temac-1.00.a";
device_type = "network";
interrupt-parent = <&xps_intc_0>;
interrupts = < 2 2 >;
llink-connected = <&DMA0>;
local-mac-address = [ 00 0a 35 99 e0 00 ];
reg = < 0x81880000 0x40 >;
xlnx,avb = <0x0>;
xlnx,bus2core-clk-ratio = <0x1>;
xlnx,mcast-extend = <0x0>;
xlnx,phy-type = <0x1>;
xlnx,phyaddr = <0x7>;
xlnx,rxcsum = <0x1>;
xlnx,rxfifo = <0x8000>;
xlnx,rxvlan-strp = <0x0>;
xlnx,rxvlan-tag = <0x0>;
xlnx,rxvlan-tran = <0x0>;
xlnx,stats = <0x0>;
xlnx,temac-type = <0x0>;
xlnx,txcsum = <0x1>;
xlnx,txfifo = <0x8000>;
xlnx,txvlan-strp = <0x0>;
xlnx,txvlan-tag = <0x0>;
xlnx,txvlan-tran = <0x0>;
} ;
} ;
RS232_Uart_1: serial@84000000 {
clock-frequency = <125000000>;
compatible = "xlnx,xps-uartlite-1.01.a", "xlnx,xps-uartlite-1.00.a";
current-speed = <9600>;
device_type = "serial";
interrupt-parent = <&xps_intc_0>;
interrupts = < 0 0 >;
port-number = <0>;
reg = < 0x84000000 0x10000 >;
xlnx,baudrate = <0x2580>;
xlnx,data-bits = <0x8>;
xlnx,family = "virtex5";
xlnx,odd-parity = <0x0>;
xlnx,use-parity = <0x0>;
} ;
rtio_tim_gn_0: rtio-tim-gn@c6400000 {
compatible = "xlnx,rtio-tim-gn-1.00.a";
reg = < 0xc6400000 0x10000 >;
xlnx,family = "virtex5";
xlnx,include-dphase-timer = <0x1>;
} ;
xps_bram_if_cntlr_1: xps-bram-if-cntlr@fffe0000 {
compatible = "xlnx,xps-bram-if-cntlr-1.00.b", "xlnx,xps-bram-if-cntlr-1.00.a";
reg = < 0xfffe0000 0x20000 >;
xlnx,family = "virtex5";
} ;
xps_intc_0: interrupt-controller@81800000 {
#interrupt-cells = <0x2>;
compatible = "xlnx,xps-intc-2.01.a", "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = < 0x81800000 0x10000 >;
xlnx,kind-of-intr = <0x1>;
xlnx,num-intr-inputs = <0x5>;
} ;
} ;
}  ;

 

 

 

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4 Replies
linnj
Xilinx Employee
Xilinx Employee
4,208 Views
Registered: ‎09-10-2008

Hi,

 

This is a tricky one since it works part of the time.  The device tree lost all of it's hierarchy when it was pasted in so it's a bit hard to review, but I don't see anything obvious.

 

If you have an ML507 Xilinx board that would be best to use to get a baseline with the Xilinx provided reference design.  With your own h/w design it's difficult to say.

 

What have you done to debug this?  Are you confident the rest of the system is performing correctly when the ethernet is not (normal performance)? 

 

Does this system meeting timing?  I would assume so as it's a small system in that device and it's pretty low frequency. 

 

An easier measure to debug might be the ping response time when you ping it. Do you see it any different in the bad case?

 

I would take out all other drivers that are not required to do this also.  Only have the uart, intc and ethernet.  This may help isolate the problem. 

 

Do you see anthing different when the drivers configure during the boot when it's not working?

 

I would assume you are doing this point to point rather thru a switch or large net, if not then I would do that to remove all the variables.

 

Sorry there's no easy answer, keep debugging.

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mathew.e
Visitor
Visitor
4,196 Views
Registered: ‎02-02-2011

Hi John,

 

Thanks for your reply. This time I have attached the dts file also.

 

There isn't any difference in the boot log when bandwidth is low.

 

We already tried putting the system in network as well as back to back. Still the behaviour is same. 

 

 We ported the setup for our custom board from the Xilinx provided reference design(xapp1140).

 

I will continue debugging as per your suggestions.

 

Regards

Mathew

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linnj
Xilinx Employee
Xilinx Employee
4,172 Views
Registered: ‎09-10-2008

Hi Mathew,

 

This maybe a tangent, but is another alternative to try.

 

So I'm also assuming that you're using the Xilinx LL TEMAC driver from our tree that is not in the mainline. I know this is a bit confusing and my apologies, but it's open source.  There is a newer driver in the mainline and in our tree such that there are really 2 LL TEMAC drivers.

 

The newer one came from the open source community because our old one was not designed to be accepted into the mainline (very old and hierarchical).  I have used it some and contributed some to getting it to where it could be a replacement for ours (and get rid of ours to reduce the confusion).

 

In the kernel config, you'll see Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver which is the newer flat driver, source code is ll_temac*.*. 

 

If you see the same issues with both drivers, I would wonder if you have a h/w or system issue.

 

Thanks.

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mathew.e
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Registered: ‎02-02-2011

Hi, 

Sorry for the late reply.

I tried with the Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) drive. This is case the behaviour is different.....

In the kernel log the ipaddress(static)  is assigned to the board, but not able to ping after booting is complete. 

THe bandwidth test is showing 0.00Mbits/s.

I did "ifconfig eth0 172.16.10.100 up". But it is showing only  "net eth0: promiscuous mode disabled".

 

Regards

Mathew

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