08-02-2016 09:17 AM
zynq will have mdio bus to configure 3 PHY modules, 1 ethernet switch and 1 PCIe switch.
2 PHY - 88E1512 probably wont need any configuration change - will work exactly as on EVB.
1 PHY - 88E1512 will have to be configured as RGMII to SGMII protocol converter.
and i need to have the ability to configure both swithces via MDIO bus.
can please someone direct me to any documentation on how to work with mdio-bus module?
08-03-2016 12:21 AM
thank you for replying.
i need to provide the ability to change configuration (via configuration menu which is written by me) at run-time - if its possible.
10-02-2019 01:09 PM
You can use phytool (Can be enabled in the petalinux-config -c rootfs)
Or you can manually access the MDIO via the phy management register. 0xff0e0034 (assuming using GEM3 on zynq ultrascale)
10-02-2019 01:18 PM
I see no results when I search for "phytool" in the rootfs config (or the kernel config, for that matter.)
Using the Phy management register sounds promising. I've found the page that describes it, but the instructions on that page require the link to be down. The use case I am interested in is run-time configuration of the Phy, without disrupting the connection.
10-02-2019 01:45 PM
To add phytool:
#Note: Mention Each package in individual line
# cascaded representation with line breaks are not valid in this file.
IMAGE_INSTALL_append = " peekpoke"
IMAGE_INSTALL_append = " gpio-demo"
IMAGE_INSTALL_append = " phytool"
petalinux-config -c rootfs
You can read the phy registers while the link is up too. Not sure why I said that in the wiki
If you where to create your own app here, this could be the best way. The wiki shows how to do a read/write.
You can mmap this.
10-02-2019 06:17 PM
Writing to the base register (the first step of the instructions on the wiki) results in networking of my machine failing. I assume I am turning off the Phy recieve and transmit bits when I do this, thus killing the network connection:
devmem 0xff0e0000 32 0x00000010
I can query the value safely, and I see 0x10001C there. The bit already seems to be set correctly, so I am skipping this step.
The next instruction line,
devmem 0xff0e0034 32 0x66020000
claims that 0110011000000100000000000000000 = 66020000hex, which it does not. I assume there is a typo here somewhere, but I do not know which side to trust. I can query 0xff0e0034, and I see the value as 0x661201e1.
10-07-2019 12:50 PM - edited 10-07-2019 12:51 PM
For anyone else wondering about this, follow the phy_management register description in the linked wiki page.
This is how you construct commands:
Initial: 0 (always) Clause (clause 22): 1 (0 for clause 45) Operation (read 22): 10 (write bits will depend on clause) phy C = 01100 (5 bits) Register 0x1 = 00001 (5 bits) Start of data: 10 (always) Value (none, read): = 0000000000000000
01100110000001100000000000000000 = 0x66060000
Clause 45 version: 00100110000001100000000000000000 = 0x26060000
Then read the phy management register (0xff0e0034) and check bit 2 to see the result.
0 means no link, 1 means active link.
I was able to read/write these values directly using an mmap. I never got results from my read commands, but I could write just fine.