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Registered: ‎03-31-2020

MIG VCU DDR4 for PL side - video_m2m: DMA initialization failed


I intend to use PL DDR4 for VCU decoder. However, debugging PL DDR4 is something too difficult for me (I could not find much documents on this, and this is also complex to debug), I meet the following error during petalinux kernel boot. Could you please guide me a hint to debug this case?

Target board: ZCU104

Platform: 2019.1

[    7.101470] xlnx_ctrl-frmb a2000000.fbwr: FrameBuffer control driver success!
[    7.108840] xlnx_ctrl-frmb a2010000.fbrd: FrameBuffer control driver success!
[    7.116233] xlnx_vpss a2200000.vpss: Xlnx VPSS control driver initialized!
[    7.123232] xilinx-mem2mem amba_pl@0:video_m2m: DMA initialization failed
[    7.130011] xilinx-mem2mem amba_pl@0:video_m2m: DMA initialization failed
[    7.136966] xilinx-mem2mem amba_pl@0:video_m2m: DMA initialization failed
[    7.143760] xilinx-mem2mem amba_pl@0:video_m2m: DMA initialization failed
[    7.152916] rtc_zynqmp ffa60000.rtc: setting system clock to 2020-06-02 11:23:59 UTC (1591097039)
[    7.161784] of_cfs_init
[    7.164234] of_cfs_init: OK
[    7.167150] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    7.206047] mmc0: new high speed SDHC card at address 5048
[    7.212040] mmcblk0: mmc0:5048 SD16G 14.4 GiB 
[    7.218108]  mmcblk0: p1 p2
[    7.221627] xilinx-mem2mem amba_pl@0:video_m2m: DMA initialization failed
[    7.228409] xilinx-mem2mem amba_pl@0:video_m2m: DMA initialization failed
[    7.306502] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    7.313027] clk: Not disabling unused clocks

I think this is from video_m2m, which is from the following pl.dtsi:

video_m2m {
				compatible = "xlnx,mem2mem";
				dmas = <&ctrlfbrd 0>, <&ctrlfbwr 0>;
				dma-names = "tx", "rx";

	vcu_ddr4_controller_0: vcu_ddr4_controller@4800000000  {
		compatible = "xlnx,ddr4-2.2";
		reg = <0x00000048 0x00000000 0x0 0x80000000>;
		#address-cells = <2>;
		#size-cells = <2>;

		plmem_vcu_dec: pool@0 {
		        reg = <0x48 0x00000000 0x0 0x70000000>;

vcu_0: vcu@a2100000 {
		#clock-cells = <1>;
		#address-cells = <2>;
		#size-cells = <2>;
		clock-names = "pll_ref", "aclk", "vcu_core_enc", "vcu_core_dec", "vcu_mcu_enc", "vcu_mcu_dec";
		clocks = <&misc_clk_1>, <&zynqmp_clk 71>, <&vcu_0 1>, <&vcu_0 2>, <&vcu_0 3>, <&vcu_0 4>;
		compatible = "xlnx,vcu-1.2", "xlnx,vcu";
		interrupt-names = "vcu_host_interrupt";
		interrupt-parent = <&gic>;
		interrupts = <0 111 4>;
		ranges ;
		reg = <0x0 0xa2140000 0x0 0x1000>,
			<0x0 0xa2141000 0x0 0x1000>;
		reg-names = "vcu_slcr", "logicore";		
		decoder {
			xlnx,dedicated-mem = <&plmem_vcu_dec>;		


ctrlfbwr: fbwr@0xa2000000 {
		compatible = "xlnx,ctrl-fbwr-1.0";
		#dma-cells = <1>;
		reg = <0x0 0xa2000000 0x0 0x10000>;
                reset-gpios = <&gpio 82 1>;
		xlnx,dma-addr-width = <32>;
ctrlfbrd: fbrd@0xa2010000 {
		compatible = "xlnx,ctrl-fbrd-1.0";
		#dma-cells = <1>;
		reg = <0x0 0xa2010000 0x0 0x10000>;
                reset-gpios = <&gpio 81 1>;
		xlnx,dma-addr-width = <32>;

The ctrlfbrd and ctrlfbwr is connected via a VPSS IP block as in the below picture.

Moreover, attached is my address editor. I am still wondering if VCU_DDR_PORT3 and VCU_DDR_PORT4 must be assigned without overlap, though in the VCU TRD, they are on the same offset.

My PL DDR inserted on the SODIMM socket is SK Hynix HMA451S6AFR8N ( So is it correct that I choose the DRAM configuration as KVR21SE15S8/4; data rate 2133?

I have tried with the ZCU104 self test BIST but did not find the error.

Thank you a lot in advance!

Screenshot from 2020-06-02 18-33-38.pngScreenshot from 2020-06-02 18-35-21.png




Screenshot from 2020-06-02 18-33-38.png
Screenshot from 2020-06-02 18-35-21.png
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2 Replies
Registered: ‎11-09-2015

Hi @peakpeak 

The memory part you are using is not part of the supported memory parts listed in PG252 p71 (table 6-10). So from a VCU Controller Point of view, you will get no support from Xilinx.

I am moving your topic to the Embedded Linux board in case anybody from the community has some tips from the linux side

Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎03-31-2020

Hi @florentw,

Thank you for your response. Could you please give me some hints on the other aspects, given that the SODIMM RAM is the compatible one? There're several questions I think would be beneficial for other beginners as well...

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