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icefish711
Observer
Observer
3,741 Views
Registered: ‎07-26-2009

MPMC problem in device tree in porting linux

hi,

   I want porting linux-2.6-xlnx(whihc is linux2.6.28) into virtex-II Pro board. When I  use  C_MPMC_BASEADDR to 0xE0000000, the system works well.

Howerver when  changed the C_MPMC_BASEADDR to 0xE0000000, compile the kernel image and download into board, error comes up from xmd console:

----error----

     I-side Memory Access check Failed, secetion 0x00400000-0x00408d33 Not accessible from processor I-sides.

----error----

    I notice that  the  file "boot/arch/boot/wrapper"   make the link_address to be 0x00400000. So I change all the 0x00400000 to be 0xe0400000 in order to mach my MPMC address in device tree.

   Then all the complie process goes well and download the kernel into board, It will work right. However, run the kernel, no information comes out through serial port. It seems the cpu stop at oxe0400070 and never go on.

   So i wonder MPMC address have to start from 0x0?  

  can anybody help me to solve this problem, so I can use MPMC not address from 0x0, rather from base address of 0xe0000000.Thx 

 

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2 Replies
Anonymous
Not applicable
3,738 Views

Hi,

 

The MPMC base address, which in your case seems to be 0xE0000000.

 

Make sure that in XMD you can do:

mwr 0xE0000000 0xEAEA

then do

mrd 0XE0000000

to see if the data wrote - this should work.

 

Make sure you check the baud rates match.  Make sure your dts file has the correct settings

 

...
       chosen {
                bootargs = "console=ttyS0,115200n8 rdinit=/init";
                linux,stdout-path = &xps_uart16550_0;
        } ;

...

 

ttyS0 is for uartnts - xps_uart16550  (not uartlite).  if you're using uartlite then you'll need different settings - I don't use this so I can't really help with this.

 

Ensure your linker script is pointing to the correct places.

 

This is really scratching the surface of the different things that can cause the kernel boot to hang... you may also find information at the link below, although it is aimed at the Microblaze, and not the powerpc which I believe is what you use on the virtex II pro...

http://fusion.phys.tue.nl/fpga/doku.php?id=fpgaworkshop2011

 

Good luck,

 

Billy.

 

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icefish711
Observer
Observer
3,729 Views
Registered: ‎07-26-2009

Thx for reply.

  I do can write data and read data from XMD, which means SDRAM works well. I use uartlite so my bootargs is

 

  bootargs = "console=ttyUL0 root=/dev/ram";

  linux,stdout-path = "/plb@0/serial@84000000";

 

DDR_SDRAM: memory@e0000000 {

  device_type = "memory";

  reg = < 0xe0000000 0x8000000 >;

 } ;

if have no modification on  linux-2.6-xlnx/arch/powerpc/boot/wrapper, I have download problem since wrapper put the link address of memory start from 0x00400000.

 

so i changed them to 0xe040000 to match memory in my dts, it solves the download problem.

but  when I compile the kernel and run it, it have no output.

it seems stop at 0xe0400070, and never go on. becuse I run and stop problem, process will always stop at that address. So I guess this is a error in boot.

 

everythings goes well if I use DDR_SDRAM 0x0 and have no modification on wrapper on Virtex-II pro board. so I wonder when to past the DDR_SDRAM parameters into linux? It seems to I have to put the DDR_SDRAM adderss from 0x0. That will not mactch my needs. Does some files need to modified to solve this problem since I have very litter experience in linux.

******

in doucment/powerpc/bootwrapper.txt, simepleImage makes is that RAM is correctly initialized and that the MMU is either off or has RAM mapped to base address 0. makes is that RAM is correctly initialized and that the MMU is either off or has RAM mapped to base address 0.

That may be the problem. 

Is there anyway to use memory not mapped to base address 0???

 

 

-------------------------------------

/*

 * Device Tree Generator version: 1.3

 *

 * (C) Copyright 2007-2008 Xilinx, Inc.

 * (C) Copyright 2007-2009 Michal Simek

 *

 * Michal SIMEK <monstr@monstr.eu>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 of

 * the License, or (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 *

 * CAUTION: This file is automatically generated by libgen.

 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6

 *

 * XPS project directory: dts-2

 */

 

/dts-v1/;

/ {

 #address-cells = <1>;

 #size-cells = <1>;

 compatible = "xlnx,virtex405", "xlnx,virtex";

 model = "testing";

 DDR_SDRAM: memory@e0000000 {

  device_type = "memory";

  reg = < 0xe0000000 0x8000000 >;

 } ;

 aliases {

  serial0 = &RS232_Uart_1;

 } ;

 chosen {

  bootargs = "console=ttyUL0 root=/dev/ram";

  linux,stdout-path = "/plb@0/serial@84000000";

 } ;

 cpus {

  #address-cells = <1>;

  #cpus = <0x1>;

  #size-cells = <0>;

  ppc405_0: cpu@0 {

   clock-frequency = <100000000>;

   compatible = "PowerPC,405", "ibm,ppc405";

   d-cache-line-size = <0x20>;

   d-cache-size = <0x4000>;

   dcr-access-method = "native";

   dcr-controller ;

   device_type = "cpu";

   i-cache-line-size = <0x20>;

   i-cache-size = <0x4000>;

   model = "PowerPC,405";

   reg = <0>;

   timebase-frequency = <100000000>;

   xlnx,dcr-resync = <0x0>;

   xlnx,deterministic-mult = <0x0>;

   xlnx,disable-operand-forwarding = <0x1>;

   xlnx,fastest-plb-clock = "DPLB0";

   xlnx,generate-plb-timespecs = <0x1>;

   xlnx,mmu-enable = <0x1>;

  } ;

 } ;

 plb0: plb@0 {

  #address-cells = <1>;

  #size-cells = <1>;

  compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";

  ranges ;

  DDR_SDRAM: mpmc@84800000 {

   #address-cells = <1>;

   #size-cells = <1>;

   compatible = "xlnx,mpmc-4.03.a";

   reg = < 0x84800000 0x10000 >;

  } ;

  RS232_Uart_1: serial@84000000 {

   clock-frequency = <100000000>;

   compatible = "xlnx,xps-uartlite-1.00.a";

   current-speed = <115200>;

   device_type = "serial";

   interrupt-parent = <&xps_intc_0>;

   interrupts = < 0 0 >;

   port-number = <0>;

   reg = < 0x84000000 0x10000 >;

   xlnx,baudrate = <0x1c200>;

   xlnx,data-bits = <0x8>;

   xlnx,family = "virtex2p";

   xlnx,odd-parity = <0x0>;

   xlnx,use-parity = <0x0>;

  } ;

  xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {

   compatible = "xlnx,xps-bram-if-cntlr-1.00.a";

   reg = < 0xffff0000 0x10000 >;

   xlnx,family = "virtex2p";

  } ;

  xps_intc_0: interrupt-controller@81800000 {

   #interrupt-cells = <0x2>;

   compatible = "xlnx,xps-intc-1.00.a";

   interrupt-controller ;

   reg = < 0x81800000 0x10000 >;

   xlnx,kind-of-intr = <0x1>;

   xlnx,num-intr-inputs = <0x1>;

  } ;

 } ;

 xlnx,compound@1 {

  #address-cells = <1>;

  #size-cells = <1>;

  compatible = "xlnx,xlnx,compound";

  ranges ;

 } ;

}  ;

 

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