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sitting
Explorer
Explorer
342 Views
Registered: ‎05-04-2014

[MPSoC] USB 3.0 eye diagram tool

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Hi,

We want to measure the eye diagram of usb 3.0 on our custom board. Does Xilinx provide the linux tool to measure it?

 

Thanks

Sitting

 

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lettertu
Xilinx Employee
Xilinx Employee
250 Views
Registered: ‎06-02-2017

(1) Bring the core out of reset =>  Load FSBL with USB3.0 setting

(2) Set GCTL.PORTCAPDIR = 1 => 0xFE20C110 = PRTCAPDIR[13:12]=0x1 - PRTCAPDIR: Port Capability Direction (PrtCapDir) - 2'b01: for Host configurations


(3)PORTSC &= 0xFFFE_FE1F  -> 0xFE20_0430
PORTSC |= 0x0001_0140 -> 0xFE20_0430
wait for some time
(4)Set GUSB2PIPECTL.HstPrtCmpl = 1 -> 0xFE20_C2C0[30] = 1, this will make the controller generate CP0 pattern.

Start the next compliance pattern:
Set GUSB2PIPECTL.HstPrtCmpl = 0
Set GUSB2PIPECTL.HstPrtCmpl = 1

View solution in original post

1 Reply
lettertu
Xilinx Employee
Xilinx Employee
251 Views
Registered: ‎06-02-2017

(1) Bring the core out of reset =>  Load FSBL with USB3.0 setting

(2) Set GCTL.PORTCAPDIR = 1 => 0xFE20C110 = PRTCAPDIR[13:12]=0x1 - PRTCAPDIR: Port Capability Direction (PrtCapDir) - 2'b01: for Host configurations


(3)PORTSC &= 0xFFFE_FE1F  -> 0xFE20_0430
PORTSC |= 0x0001_0140 -> 0xFE20_0430
wait for some time
(4)Set GUSB2PIPECTL.HstPrtCmpl = 1 -> 0xFE20_C2C0[30] = 1, this will make the controller generate CP0 pattern.

Start the next compliance pattern:
Set GUSB2PIPECTL.HstPrtCmpl = 0
Set GUSB2PIPECTL.HstPrtCmpl = 1

View solution in original post