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Visitor smee204
Visitor
11,185 Views
Registered: ‎02-06-2012

Micrel ethernel phy - unable to generate target frequency

We have built a custom board using the Micrel KSZ9021 ethernet phy. The board has been designed to run at 100M only so the ethernet clock in vivaldo was set to 25MHz.

 

I have enabled the phy in the kernel and device tree however during boot we continouly get messages saying:

 macb e000b000.ps7-ethernet eth0: unable to generate target frequency: 25000000 Hz

I have checked and the output of cll_round_rate is 0Hz. This does not seem correct!

Is this because we are running our zynq off a 50MHz clock?

In the device tree I had to change the ps7_slcr ps-clk-frequency to 50000000.

 

Here is the ps7-ethernet section of the device tree.

ps7_ethernet_0: ps7-ethernet@e000b000 {
			phy-handle = <&phy0>;
			phy-mode = "rgmii-id";			
			mdio {
				phy0: phy@1 {
					compatible = "micrel,ksz9021";
					device_type = "ethernet-phy";
					reg = <1>;
					max-speed = <100>;
				} ;
			} ;
		} ;

 Is there any other clocks I need to change?

 

Thanks

 

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4 Replies
Xilinx Employee
Xilinx Employee
11,182 Views
Registered: ‎03-13-2012

Re: Micrel ethernel phy - unable to generate target frequency

The change of the oscillator should be enough. Check that clock hierarchy and frequencies match your expectations:

cat /sys/kernel/debug/clk/clk_summary

 My first suspect for the zero frequency would be a misconfigured mux in the clock hierarchy.

Visitor smee204
Visitor
11,178 Views
Registered: ‎02-06-2012

Re: Micrel ethernel phy - unable to generate target frequency

Thanks for the quick reply. How do I set the mux?

 

Here is my clk_summary:

 clock                         enable_cnt  prepare_cnt        rate   accuracy
--------------------------------------------------------------------------------
 ps_clk                                   3            3    50000000          0
    iopll_int                             1            1  1000000000          0
       iopll                              7            7  1000000000          0
          dbg_mux                         1            1  1000000000          0
             dbg_div                      1            1    66666667          0
                dbg_emio_mux              1            1    66666667          0
                   dbg_trc                1            1    66666667          0
          can_mux                         0            0  1000000000          0
             can_div0                     0            0    40000000          0
                can_div1                  0            0     8000000          0
                   can1_gate              0            0     8000000          0
                      can1                0            0     8000000          0
                   can0_gate              0            0     8000000          0
                      can0                0            0     8000000          0
          gem1_mux                        0            0  1000000000          0
             gem1_div0                    0            0    16666667          0
                gem1_div1                 0            0    16666667          0
                   gem1_emio_mux           0            0    16666667          0
                      gem1                0            0    16666667          0
          gem0_mux                        0            0  1000000000          0
             gem0_div0                    0            0  1000000000          0
                gem0_div1                 0            0  1000000000          0
          spi0_mux                        0            0  1000000000          0
             spi0_div                     0            0   166666667          0
                spi1                      0            0   166666667          0
                spi0                      0            0   166666667          0
          uart0_mux                       1            1  1000000000          0
             uart0_div                    1            1   100000000          0
                uart1                     0            0   100000000          0
                uart0                     1            1   100000000          0
          sdio0_mux                       1            1  1000000000          0
             sdio0_div                    1            1   125000000          0
                sdio1                     0            0   125000000          0
                sdio0                     1            1   125000000          0
          pcap_mux                        0            0  1000000000          0
             pcap_div                     0            0   200000000          0
                pcap                      0            0   200000000          0
          lqspi_mux                       0            0  1000000000          0
             lqspi_div                    0            0   200000000          0
                lqspi                     0            0   200000000          0
          fclk3_mux                       1            1  1000000000          0
             fclk3_div0                   1            1    50000000          0
                fclk3_div1                1            1    50000000          0
                   fclk3                  1            1    50000000          0
          fclk2_mux                       1            1  1000000000          0
             fclk2_div0                   1            1    50000000          0
                fclk2_div1                1            1    50000000          0
                   fclk2                  1            1    50000000          0
          fclk1_mux                       1            1  1000000000          0
             fclk1_div0                   1            1    50000000          0
                fclk1_div1                1            1    50000000          0
                   fclk1                  1            1    50000000          0
          fclk0_mux                       1            1  1000000000          0
             fclk0_div0                   1            1   100000000          0
                fclk0_div1                1            1   100000000          0
                   fclk0                  1            1   100000000          0
    ddrpll_int                            1            1  1050000000          0
       ddrpll                             3            3  1050000000          0
          dci_div0                        1            1    20192308          0
             dci_div1                     1            1    10096154          0
                dci                       1            1    10096154          0
          ddr3x_div                       1            1   525000000          0
             ddr3x                        1            1   525000000          0
          ddr2x_div                       1            1   350000000          0
             ddr2x                        1            1   350000000          0
    armpll_int                            1            1  1300000000          0
       armpll                             1            1  1300000000          0
          smc_mux                         0            0  1300000000          0
             smc_div                      0            0    21666667          0
                smc                       0            0    21666667          0
          cpu_mux                         1            1  1300000000          0
             cpu_div                      3            3   650000000          0
                cpu_1x_div                1            1   108333333          0
                   cpu_1x                 8            8   108333333          0
                      smc_aper            0            0   108333333          0
                      lqspi_aper           0            0   108333333          0
                      gpio_aper           1            1   108333333          0
                      uart1_aper           0            0   108333333          0
                      uart0_aper           1            1   108333333          0
                      i2c1_aper           0            0   108333333          0
                      i2c0_aper           0            0   108333333          0
                      can1_aper           0            0   108333333          0
                      can0_aper           0            0   108333333          0
                      spi1_aper           0            0   108333333          0
                      spi0_aper           0            0   108333333          0
                      sdio1_aper           0            0   108333333          0
                      sdio0_aper           1            1   108333333          0
                      gem1_aper           0            0   108333333          0
                      gem0_aper           2            2   108333333          0
                      usb1_aper           0            0   108333333          0
                      usb0_aper           2            2   108333333          0
                      dbg_apb             1            1   108333333          0
                      swdt                0            0   108333333          0
                cpu_2x_div                1            1   216666666          0
                   cpu_2x                 1            1   216666666          0
                      dma                 1            1   216666666          0
                cpu_3or2x_div             1            1   325000000          0
                   cpu_3or2x              2            2   325000000          0
                cpu_6or4x                 0            0   650000000          0
 can1_mio_mux                             0            0           0          0
 can0_mio_mux                             0            0           0          0
 gem0_emio_mux                            1            1           0          0
    gem0                                  1            1           0          0

 

Thanks

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Xilinx Employee
Xilinx Employee
11,170 Views
Registered: ‎03-13-2012

Re: Micrel ethernel phy - unable to generate target frequency

Looks like you selected an external clock via EMIO for the GEM. This is set in PCW in Vivado (somewhere around where you set the frequency as well).

You need to fix that, export the HW again and update the FSBL accordingly. (for a quick test it should work if you just manually set the mux correctly from the U-Boot command line.

Visitor smee204
Visitor
11,163 Views
Registered: ‎02-06-2012

Re: Micrel ethernel phy - unable to generate target frequency

Thanks that fixed the error message.

It now boots into Linux with no error messages however the ethernet does not work. It detects the link is up but I can not get a dhcp address and using a static ip address does not work.

Any idea what I can do to debug this?

 

Thanks

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