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liyafeng007
Contributor
Contributor
7,395 Views
Registered: ‎04-07-2008

Microblaze linux boot hangs after "Freeing unused kernel memory"

 I am porting linux on Spartan3A DSP 1800 board

 

I use XMD to download the image

 

The kernel stop at :Freeing unused kernel memory: 933k freed

I used 

make ARCH=microblaze xilinx_mmu_defconfig

and just changed "Physical address where Linux Kernel is" to 0x88000000 where the DDR base address is.


 

I have search the forum about the problem. A few post mentioned the same problem, but i still get no idea.


so, need  help.


This is the console output:



early_printk_console is enabled at 0x84000000
Ramdisk addr 0x00000003, Compiled-in FDT at 0xc02a3d68
Linux version 2.6.35 (lyf@lyf-desktop) (gcc version 4.1.2) #10 Mon Jan 10 17:04:
08 CST 2011
setup_cpuinfo: initialising
setup_cpuinfo: No PVR support. Using static CPU info from FDT
cache: wt_msr
setup_memory: max_mapnr: 0x8000
setup_memory: min_low_pfn: 0x88000
setup_memory: max_low_pfn: 0x90000
On node 0 totalpages: 32768
free_area_init_node: node 0, pgdat c033d2a4, node_mem_map c0439000
  Normal zone: 256 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 32512 pages, LIFO batch:7
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
Kernel command line: console=ttyUL0 root=/dev/ram
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 125492k/131072k available
Hierarchical RCU implementation.
        RCU-based detection of stalled CPUs is disabled.
        Verbose stalled-CPUs detection is disabled.
NR_IRQS:32
xlnx,xps-intc-1.00.a #0 at 0xc8000000, num_irq=2, edge=0x1
xlnx,xps-timer-1.00.a #0 at 0xc8004000, irq=1
microblaze_timer_set_mode: shutdown
microblaze_timer_set_mode: periodic
Calibrating delay loop... 30.31 BogoMIPS (lpj=151552)
pid_max: default: 4096 minimum: 301
Mount-cache hash table entries: 512
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
XGpio: /plb@0/gpio@81400000: registered
XGpio: /plb@0/gpio@81420000: registered
XGpio: /plb@0/gpio@81440000: registered
Switching to clocksource microblaze_clocksource
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP reno registered
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
GPIO pin is already allocated
Slow work thread pool: Starting up
Slow work thread pool: Ready
msgmni has been set to 245
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
84000000.serial: ttyUL0 at MMIO 0x84000000 (irq = 0) is a uartlite
console [ttyUL0] enabled
brd: module loaded
Xilinx SystemACE device driver, major=254
xilinx-xps-spi 82828000.xps-spi: no IRQ found
xilinx_emaclite 81000000.ethernet: Device Tree Probing
xilinx_emaclite 81000000.ethernet: no IRQ found
xilinx_emaclite: probe of 81000000.ethernet failed with error -1
i2c /dev entries driver
TCP cubic registered
NET: Registered protocol family 17
Freeing unused kernel memory: 933k freed

 

 

 

 

Thanks!

 

 

 


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7 Replies
liyafeng007
Contributor
Contributor
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Registered: ‎04-07-2008

And the kernel config list

 

 

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liyafeng007
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Contributor
7,392 Views
Registered: ‎04-07-2008

And my dts file

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liyafeng007
Contributor
Contributor
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Registered: ‎04-07-2008

MHS file


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Thu Dec 23 16:40:22 2010
# Target Board: Xilinx Spartan-3A DSP 1800A Starter Board Rev 1
# Family: spartan3adsp
# Device: xc3sd1800a
# Package: fg676
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 62.50 MHz
# On Chip Memory : 8 KB
# Total Off Chip Memory : 128 MB
# - DDR2_SDRAM = 128 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0


PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC = [0:7]
PORT fpga_0_Push_Buttons_GPIO_in_pin = fpga_0_Push_Buttons_GPIO_in, DIR = I, VEC = [0:3]
PORT fpga_0_DIP_Switches_8Bit_GPIO_in_pin = fpga_0_DIP_Switches_8Bit_GPIO_in, DIR = I, VEC = [0:7]
PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr, DIR = O, VEC = [12:0]
PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DDR2_BankAddr, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM, DIR = O, VEC = [3:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS, DIR = IO, VEC = [3:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n, DIR = IO, VEC = [3:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ, DIR = IO, VEC = [31:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I, DIR = I
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O, DIR = O
PORT fpga_0_SPI_FLASH_MISO_pin = fpga_0_SPI_FLASH_MISO, DIR = IO
PORT fpga_0_SPI_FLASH_MOSI_pin = fpga_0_SPI_FLASH_MOSI, DIR = IO
PORT fpga_0_SPI_FLASH_SCK_pin = fpga_0_SPI_FLASH_SCK, DIR = IO
PORT fpga_0_SPI_FLASH_SS_pin = fpga_0_SPI_FLASH_SS, DIR = IO, VEC = [0:4]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 7.10.d
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_FAMILY = spartan3adsp
PARAMETER C_INSTANCE = microblaze_0
PARAMETER C_USE_MMU = 3
PARAMETER C_MMU_TLB_ACCESS = 2
PARAMETER C_MMU_ZONES = 2
PARAMETER C_USE_ICACHE = 1
PARAMETER C_ICACHE_BASEADDR = 0x88000000
PARAMETER C_ICACHE_HIGHADDR = 0x88FFFFFF
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BASEADDR = 0x88000000
PARAMETER C_DCACHE_HIGHADDR = 0x88FFFFFF
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
BUS_INTERFACE DXCL = microblaze_0_DXCL
BUS_INTERFACE IXCL = microblaze_0_IXCL
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
PORT MB_RESET = mb_reset
PORT INTERRUPT = microblaze_0_INTERRUPT_0
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.03.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
PORT Bus_Error_Det = mb_plb_Bus_Error_Det
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 62500000
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
PORT Interrupt = RS232_Uart_1_Interrupt
END

BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END

BEGIN xps_gpio
PARAMETER INSTANCE = Push_Buttons
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = fpga_0_Push_Buttons_GPIO_in
END

BEGIN xps_gpio
PARAMETER INSTANCE = DIP_Switches_8Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = fpga_0_DIP_Switches_8Bit_GPIO_in
END

BEGIN xps_ethernetlite
PARAMETER INSTANCE = Ethernet_MAC
PARAMETER HW_VER = 2.00.b
PARAMETER C_SPLB_CLK_PERIOD_PS = 16000
PARAMETER C_BASEADDR = 0x81000000
PARAMETER C_HIGHADDR = 0x8100ffff
BUS_INTERFACE SPLB = mb_plb
PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
END

BEGIN mpmc
PARAMETER INSTANCE = DDR2_SDRAM
PARAMETER HW_VER = 4.03.a
PARAMETER C_MEM_PARTNO = MT47H32M16-5E
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_MEM_CLK_WIDTH = 2
PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000
PARAMETER C_PIM1_BASETYPE = 1
PARAMETER C_PIM2_BASETYPE = 1
PARAMETER C_NUM_PORTS = 3
PARAMETER C_MPMC_BASEADDR = 0x88000000
PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
BUS_INTERFACE SPLB0 = mb_plb
BUS_INTERFACE XCL2 = microblaze_0_DXCL
BUS_INTERFACE XCL1 = microblaze_0_IXCL
PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT
PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr
PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr
PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n
PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE
PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n
PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n
PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n
PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk
PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n
PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM
PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS
PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n
PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ
PORT DDR2_DQS_Div_I = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I
PORT DDR2_DQS_Div_O = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O
PORT MPMC_Clk0 = DDR2_SDRAM_mpmc_clk_s
PORT MPMC_Clk90 = DDR2_SDRAM_mpmc_clk_90_s
PORT MPMC_Rst = sys_periph_reset
END

BEGIN xps_spi
PARAMETER INSTANCE = SPI_FLASH
PARAMETER HW_VER = 2.00.b
PARAMETER C_FIFO_EXIST = 1
PARAMETER C_SCK_RATIO = 64
PARAMETER C_NUM_SS_BITS = 5
PARAMETER C_BASEADDR = 0x82828000
PARAMETER C_HIGHADDR = 0x8282807f
BUS_INTERFACE SPLB = mb_plb
PORT SPISEL = net_vcc
PORT MISO = fpga_0_SPI_FLASH_MISO
PORT MOSI = fpga_0_SPI_FLASH_MOSI
PORT SCK = fpga_0_SPI_FLASH_SCK
PORT SS = fpga_0_SPI_FLASH_SS
PORT IP2INTC_Irpt = SPI_FLASH_IP2INTC_Irpt
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 125000000
PARAMETER C_CLKOUT0_FREQ = 62500000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT1_FREQ = 125000000
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = DCM0
PARAMETER C_CLKOUT2_FREQ = 125000000
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT2_PHASE = 90
PARAMETER C_CLKOUT2_GROUP = DCM0
PORT CLKOUT0 = sys_clk_s
PORT CLKOUT1 = DDR2_SDRAM_mpmc_clk_s
PORT CLKOUT2 = DDR2_SDRAM_mpmc_clk_90_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END

BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.d
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x86208000
PARAMETER C_HIGHADDR = 0x86209fff
BUS_INTERFACE SPLB = mb_plb
PORT Intr = xps_timer_0_Interrupt&RS232_Uart_1_Interrupt
PORT Irq = microblaze_0_INTERRUPT_0
END

BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = xps_timer_0_Interrupt
END
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liyafeng007
Contributor
Contributor
7,347 Views
Registered: ‎04-07-2008

It seems the kernel stop at init process in main.c

 

static void run_init_process(char *init_filename)
{
    argv_init[0] = init_filename;
    kernel_execve(init_filename, argv_init, envp_init);
}

 

but how to sovle the problem?

 

Thanks!

 

 

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liyafeng007
Contributor
Contributor
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Registered: ‎04-07-2008

Now it can boot to file system.
In microblaze configuration ,an option for MMU
Enable Access to Memory Management Special Registers should set to full

 

I think this option should be added in xilinx wikidot.com, It's not mentioned there.

It's helpfull for beginer.

 

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linnj
Xilinx Employee
Xilinx Employee
7,225 Views
Registered: ‎09-10-2008

I'm sort of confused, where are you saying you made this change, to the kernel config or the h/w project?

 

Our defconfigs turn on the MMU for the kernel configuration and for the h/w project the wiki says ...

 

  • The MMU in virtual mode and 2 memory protection zones
  •  

    I'm trying to figure out what needs to be clearer.

     

    Thanks.

     

     

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    liyafeng007
    Contributor
    Contributor
    7,110 Views
    Registered: ‎04-07-2008

    Hi John

    I made this change in h/w project of MB configuration.
    I changed C_MMU_TLB_ACCESS from 2 to 3 in MHS file.
    Best Regards.
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