Hello,I am having problems with the fpga-manager-utils
When I enable FPGA Manager checkbox in petalinux-config, the project fails to build. I am not using the minized BSP, but have tried it as well with the same result.
I am compiling on Kubuntu 18.04 LTS and Petalinux 2019.1 version. The provided HDF used to configure the project has bitstream included and the DT overlay is enabled as well in the config.
I have been able to track the error up to: /Xilinx/Petalinux/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fpga-manager-util/fpga-manager-util_1.0.bb:
if [ ! -e "${RECIPE_SYSROOT}/boot/devicetree/pl.dtbo" ]; then
bbfatal "base dtbo was not generated. Check logs, make sure overlays are enabled."
fiThe Log says:ERROR: base dtbo was not generated. Check logs, make sure overlays are enabled.
Neverthless no matter what I do,the project fails and compiles only if fpga-manager is disabled. I don't want to upgrade to 2019.2 unless necessary. Any help is appreciated.
Could possibly be the cause,that my design contains only Zynq PS and no other PL parts?
Thanks
