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Visitor mihai.coca
Visitor
3,565 Views
Registered: ‎05-19-2017

Multiple AXI memory mapped busses on IP core for creating a petalinux driver

Hi,

     I'm trying to install a module driver in my petalinux rootfs for using on zedboard. I configured an IP core for PL, which has two AXI memory mapped ports (pic1). Now, for using my driver which is responsible for communications with my IP core, i need to know the conversions from phisical addresses to virtual addresses made by kernel.

At installation i see just one conversion (S00 is Lite and S01 is Full) :

root@avnet-digilent-zedboard-2017_2:/lib/modules/4.9.0-xilinx-v2017.2/extra# insmod driver-mihaiv1.ko 
[ 1324.279333] <1>Hello module world.
[ 1324.282663] <1>Module parameters were (0xdeadbeef) and "default"
[ 1324.289030] driver-mihaiv1 43c00000.accHW: Device Tree Probing
[ 1324.294839] driver-mihaiv1 43c00000.accHW: no IRQ found
[ 1324.299993] driver-mihaiv1 43c00000.accHW: driver-mihaiv1 at 0x43c00000 mapped to 0xe09c0000

In pics you can see the phisical adresses for my IP core. As i see, just the first phisical adress has a virtual conversion <0x43c00000 to 0xe09c0000>.

Has anyone met this problem?

Screenshot from 2017-07-19 18-49-04.png
Screenshot from 2017-07-19 18-48-44.png
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6 Replies
Explorer
Explorer
3,519 Views
Registered: ‎11-24-2013

Re: Multiple AXI memory mapped busses on IP core for creating a petalinux driver

Hi @mihai.coca,

 

how does your device tree node for this IP look like? How is the mapping in the code of the driver being done?

 

Regards

Ignacio

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Explorer
Explorer
3,515 Views
Registered: ‎10-14-2015

Re: Multiple AXI memory mapped busses on IP core for creating a petalinux driver

have a read at this:

http://www.xml.com/ldd/chapter/book/ch13.html

 

an alternative could be to use UIO drivers, then you mmap /dev/uio0 and access all your registers from there

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Visitor mihai.coca
Visitor
3,509 Views
Registered: ‎05-19-2017

Re: Multiple AXI memory mapped busses on IP core for creating a petalinux driver

Hi @imgignacio,

 

  Thank you for your response. My pl.dtsi is:

mihai@mihai-ThinkStation-P310:~/FPGA/accelerator/components/plnx_workspace/device-tree-generation$ more pl.dtsi 
/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Wed Jul 19 16:25:33 2017
*/


/ {
	amba_pl: amba_pl {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges ;
		accHW_0: accHW@43c00000 {
			compatible = "xlnx,accHW-1.0";
			reg = <0x43c00000 0x10000 0x4aa00000 0x10000>;
			xlnx,s00-axi-addr-width = <0x4>;
			xlnx,s00-axi-data-width = <0x20>;
			xlnx,s01-axi-addr-width = <0x6>;
			xlnx,s01-axi-aruser-width = <0x0>;
			xlnx,s01-axi-awuser-width = <0x0>;
			xlnx,s01-axi-buser-width = <0x0>;
			xlnx,s01-axi-data-width = <0x20>;
			xlnx,s01-axi-id-width = <0xc>;
			xlnx,s01-axi-ruser-width = <0x0>;
			xlnx,s01-axi-wuser-width = <0x0>;
		};
	};
};

 I do not undestand what you want to say by "the mapping in the code of the driver being done".

 

Regards,

Mihai

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Explorer
Explorer
3,503 Views
Registered: ‎11-24-2013

Re: Multiple AXI memory mapped busses on IP core for creating a petalinux driver

Hi @mihai.coca,

 

sorry, maybe my question was not so clear.

 

What I meant is:

 

The mapping of the physical memory to virtual memory is being done after loading the kernel module. That means, in the code of the kernel module there are some lines to perform this mapping (ioremap?). According to the message being plotted ("Device Tree Probing"), you are getting the addresses to map from the device tree. So maybe the code of the driver is just not taking the second address of the device tree into consideration...

 

Maybe you can also check if the second address is present on "/proc/device-tree" on your board, to be sure that the kernel interpreted it right.

 

Regards,

Ignacio

 

 

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Highlighted
Visitor mihai.coca
Visitor
3,499 Views
Registered: ‎05-19-2017

Re: Multiple AXI memory mapped busses on IP core for creating a petalinux driver

Hi @imgignacio

 

Thank you again for replying so quick. The code for mapping from probe function is the default one.

 

	/* Get iospace for the device */
	r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r_mem) {
		dev_err(dev, "invalid address\n");
		return -ENODEV;
	}
	lp = (struct driver_mihai_local *) kmalloc(sizeof(struct driver_mihai_local), GFP_KERNEL);
	if (!lp) {
		dev_err(dev, "Cound not allocate driver-mihai device\n");
		return -ENOMEM;
	}
	dev_set_drvdata(dev, lp);
	lp->mem_start = r_mem->start;
	lp->mem_end = r_mem->end;

	if (!request_mem_region(lp->mem_start,
				lp->mem_end - lp->mem_start + 1,
				DRIVER_NAME)) {
		dev_err(dev, "Couldn't lock memory region at %p\n",
			(void *)lp->mem_start);
		rc = -EBUSY;
		goto error1;
	}

	lp->base_addr = ioremap(lp->mem_start, lp->mem_end - lp->mem_start + 1);
	if (!lp->base_addr) {
		dev_err(dev, "driver-mihai: Could not allocate iomem\n");
		rc = -EIO;
		goto error2;
	}

I looked into /proc/device-tree and this is what is see.

root@avnet-digilent-zedboard-2017_2:/proc/device-tree/amba_pl/accHW@43c00000# ls
compatible                 xlnx,s01-axi-addr-width    xlnx,s01-axi-id-width
name                       xlnx,s01-axi-aruser-width  xlnx,s01-axi-ruser-width
reg                        xlnx,s01-axi-awuser-width  xlnx,s01-axi-wuser-width
xlnx,s00-axi-addr-width    xlnx,s01-axi-buser-width
xlnx,s00-axi-data-width    xlnx,s01-axi-data-width

As i see, there are some files for the second interface s01.

 

Thanks,

Mihai

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Explorer
Explorer
3,441 Views
Registered: ‎11-24-2013

Re: Multiple AXI memory mapped busses on IP core for creating a petalinux driver

Hi @mihai.coca,

 

 

since you are getting the memory range from "pdev", it would be interesting to know which value has "r_mem->end". I think the fastest way is to do (if you are noot root, with sudo):

 

cat /proc/iomem

and observe how many addresses were mapped. Another way would be to insert some "printk" in the code to plot the value of "r_mem->end".

 

Regards,

Ignacio

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