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Contributor
Contributor
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Registered: ‎09-28-2018

OSL2018.2: axi DMA test fails with kernel module axidmatest.ko

Hi Xilinx, 

I'm doing some dma testing with a loopback design. 

I receive following errors after loading the module.  TX test timed out, What does this mean?  I get the feeling it has something to do with the interrupt handler or some kind of completon flag, but I can't figure out why...

You can also see this "has errors 40" message in my dmesg output.

The manual PG021 states:  

DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. • 0 = No DMA Internal Errors • 1 = DMA Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode

 

[ 4092.552027] cma: cma_alloc(cma ffffff8008eae140, count 8, align 3)
[ 4092.552158] cma: cma_alloc(): returned ffffffbf018824c0
[ 4092.552242] cma: cma_alloc(cma ffffff8008eae140, count 1, align 0)
[ 4092.552265] cma: cma_alloc(): returned ffffffbf01881ae8
[ 4092.552301] cma: cma_alloc(cma ffffff8008eae140, count 8, align 3)
[ 4092.552325] cma: cma_alloc(): returned ffffffbf01882680
[ 4092.552375] cma: cma_alloc(cma ffffff8008eae140, count 1, align 0)
[ 4092.552396] cma: cma_alloc(): returned ffffffbf01881bc8
[ 4092.552456] dmatest: Started 1 threads using dma1chan0 dma1chan1
[ 4092.552510] xilinx-vdma a0000000.dma: Channel ffffffc87ad1a618 has errors 40, cdr 700a8000 tdr 700a8500
[ 4093.552538] xilinx-vdma a0000000.dma: Cannot start channel ffffffc87ad1a418: 80009
[ 4123.728207] dma1chan0-dma1c: #0: tx test timed out
[ 4123.728216] dma1chan0-dma1c: terminating after 1 tests, 1 failures (status 0)

The code XILINX_GITHUB: https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/axidmatest.c#L392

It seems if the send bytes never get a complete flag or interrupt back and the whole routine goes into a timeout. 

		dma_async_issue_pending(tx_chan);
		dma_async_issue_pending(rx_chan);

		tx_tmo = wait_for_completion_timeout(&tx_cmp, tx_tmo);

		status = dma_async_is_tx_complete(tx_chan, tx_cookie,
							NULL, NULL);

		if (tx_tmo == 0) {
			pr_warn("%s: #%u: tx test timed out\n",
				   thread_name, total_tests - 1);
			failed_tests++;
			continue;
		} else if (status != DMA_COMPLETE) {
			pr_warn(
			"%s: #%u: tx got completion callback, ",
				   thread_name, total_tests - 1);
			pr_warn("but status is \'%s\'\n",
				   status == DMA_ERROR ? "error" :
							"in progress");
			failed_tests++;
			continue;
		}

My device tree entry pl.dtsi

	amba_pl: amba_pl@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges ;
		axi_dma_0: dma@a0000000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
			clocks = <&clk 71>, <&clk 71>, <&clk 71>, <&clk 71>;
			compatible = "xlnx,axi-dma-1.00.a";
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&gic>;
			interrupts = <0 89 4 0 90 4>;
			reg = <0x0 0xa0000000 0x0 0x1000>;
			xlnx,addrwidth = <0x40>;
			xlnx,include-sg ;
			xlnx,sg-length-width = <0x1a>;
			dma-channel@a0000000 {
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0x1>;
				interrupts = <0 89 4>;
				xlnx,datawidth = <0x20>;
				xlnx,device-id = <0x0>;
			};
			dma-channel@a0000030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 90 4>;
				xlnx,datawidth = <0x20>;
				xlnx,device-id = <0x0>;
			};
		};
};

in my system-top I included:

	axidmatest_0: axidmatest@0 {
                     compatible ="xlnx,axi-dma-test-1.00.a";
                     dmas = <&axi_dma_0 0
                             &axi_dma_0 1>;
                     dma-names = "axidma0", "axidma1";
	};

The bitstream overview and address map are attached to this post. 

Any help or tip would be most welcome.

Thanks in advance

Deville.

 

 

block diagram.png
address map 64-bit dma.png
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