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968 Views
Registered: ‎09-30-2011

Odd behavior of AXI DMA in SG mode

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We have a zc706-based system running Linux with the Xilinx AXIDMA core instantiated in SG mode. Running the 'canned' Xilinx test failed so I wrote a small program that manually exercises the IP through /dev/mem to access the IP's registers and defines the descriptors and memory blocks for transfer and buffers for receipt. What I noticed was that the status offset field (at offset 0x1c) in the descriptors was not getting updated but the actual memory transfers were executing. That is, the data was ending up in the receive buffers. After a little snooping about, I found that the descriptor's control offset field (at offset 0x18) was getting the status value written to it.

 

After reviewing our implementation, we see no obvious race conditions on the address lines and after a review of the SG DMA operations we failed to notice anything awry.

 

I was wondering if any of you kind people had any ideas as to what might be causing this sort of unusual behavior? Or even some additional diagnostics tests we might do to isolate the problem.

 

Thanks!

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1 Solution

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1,298 Views
Registered: ‎09-30-2011

Re: Odd behavior of AXI DMA in SG mode

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OK. FWIW it looks like the issue was that the ps7_init_gpl.c file provided to me was incorrect and that the clock, MIO and DDR settings specified in it were wrong for the target board (zc706). This led to having a boot.bin that was basically unusable on that target board. So, I suppose the issue was organizational and related to not asking the right questions at the outset and making bad assumptions

 

Ah well.

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5 Replies
926 Views
Registered: ‎09-30-2011

Re: Odd behavior of AXI DMA in SG mode

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I found the issue but not the root cause. It looks like the memory map width is behaving like it was set to 64 bit instead of 32 so every other word was skipped. Now the problem is that careful review of the FPGA design indicates that the memory map widths were set to 32 and the device tree was also set to 32 bit but when I peek at the HP control registers they are all set to 64 bit.

 

Any ideas as to what might cause that?

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Xilinx Employee
Xilinx Employee
913 Views
Registered: ‎10-04-2016

Re: Odd behavior of AXI DMA in SG mode

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Hi neil@formidableengineeringconsultants.com,

Could you explain what you mean when you say that the HP control registers were set to 64 bit?

 

From what you have described, I can't tell whether this is a hardware or a software issue. The easiest way to start debugging this would be to add some system ILAs to the design and grab some traces so that we can see the AXI DMA writes back to the buffer descriptor status field. This method would tell us whether the hardware is an issue.

 

The System ILAs would be on the AXI Interfaces between the AXI DMA M_AXI_SG port and the interconnect slave port and between the Interconnect M00_AXI port and the Zynq S_AXI port. I expect AXI DMA is sending the correct write address and data, but I want to make sure that the interconnect doesn't do anything funny to the writes.

 

Regards,

 

Deanna

 

 

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Xilinx Employee
Xilinx Employee
912 Views
Registered: ‎10-04-2016

Re: Odd behavior of AXI DMA in SG mode

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Here is an example block diagram with the System ILA connections I described.

 

axiDmaSGILA.JPG

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906 Views
Registered: ‎09-30-2011

Re: Odd behavior of AXI DMA in SG mode

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Thanks for your response. I, too, can't figure out if the problem is hardware or software :-( 

 

So for more detail, the AXI DMA IP is attached to the PS through two HP ports. In the design the HP ports are set to be 32 bits wide. We have verified that looking at the settings in Vivado. We then load the design bitstream and boot the system. I wrote a little program that lets me read system registers. I can look at the HP Port control registers (TRM App B.4) AFI_RDCHAN_CTRL and AFI_WRCHAN_CTRL  bit 0 is 32BitEn and if set indicates that the port is configured to be 32 bits wide. Those values are 0. If I write a 1 to them then my DMA starts working correctly.

 

I thought the bitstream sets those up and that nothing in the kernel or driver space should touch them but maybe not?

 

I hope that helps explain my predicament

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1,299 Views
Registered: ‎09-30-2011

Re: Odd behavior of AXI DMA in SG mode

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OK. FWIW it looks like the issue was that the ps7_init_gpl.c file provided to me was incorrect and that the clock, MIO and DDR settings specified in it were wrong for the target board (zc706). This led to having a boot.bin that was basically unusable on that target board. So, I suppose the issue was organizational and related to not asking the right questions at the outset and making bad assumptions

 

Ah well.

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