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Observer vishnumotghare
Registered: ‎07-02-2014

PCLK clock not found error

Hi ,

I am trying to add qspi node in device tree. I am getting error like PCLK clock is not found


Below is my device node entry in device file,



ps7_qspi_0: ps7-qspi@0xFF00D000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "ref_clk", "pclk";
			compatible = "xlnx,usmp-gqspi", "cdns,spi-r1p6";
			stream-connected-dma = <0x11>;
			clocks = <0xc 0xc>;
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 37 4>;
			num-chip-select = <0x2>;
			reg = <0x0 0xff00d000 0x1000 0x0 0xc0000000 0x8000000>;
			speed-hz = <0xbebc200>;
			xlnx,fb-clk = <0x1>;
			xlnx,qspi-clk-freq-hz = <50000000>;
			xlnx,qspi-mode = <0x2>;

			qspi_flash_lcs_lb: qspi_flash_lcs_lb@0 {
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				compatible = "n25q128a11", "st,m25p80";
				spi-max-frequency = <0x2faf08>;
				reg = <0x0 0x0>;

				qspi_flash_lcs_lb@0x00000000 {
					label = "qspi_flash_lcs_lb";
					reg = <0x0 0x1000000>;

This is  kernel log messages i am getting at boot time,


 ERROR: could not get clock /amba@0/ps7-qspi@0xFF00D000:pclk(1)
[  141.740394] cdns-spi ff00d000.ps7-qspi: pclk clock not found.
[  141.750061] cdns-spi: probe of ff00d000.ps7-qspi failed with error -2


Device tree concept is new for me so please help.


Thanks in Advance,




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Xilinx Employee
Xilinx Employee
Registered: ‎09-10-2008

Re: PCLK clock not found error



Is this a decompiled device tree rather than the original source? Did you generate this tree with a Xilinx tool?


You didn't way what kernel version, so I'm looking at the 702 board device tree in the latest kernel to see what it looks like (arch/arm/boot/dts).


The clocks in that node appear to be referring to the same clock while that's normally not the case.  In the 702 device tree qspi node I see this.


clocks = <&clkc 10>, <&clkc 43>;
while yours is clocks = <0xc 0xc>; 
These clocks refer into the clock list (I'm no expert on the clocking) in the device tree (a snippet from the 702 below).
clkc: clkc@100 {
#clock-cells = <1>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x",
"cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci",
"lqspi", "smc", "pcap", "gem0", "gem1",
"fclk0", "fclk1", "fclk2", "fclk3", "can0",
"can1", "sdio0", "sdio1", "uart0", "uart1",
"spi0", "spi1", "dma", "usb0_aper", "usb1_aper",
"gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper",
"spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
"uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper",
"swdt", "dbg_trc", "dbg_apb";
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
ps-clk-frequency = <33333333>;
reg = <0x100 0x100>;
} ;


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