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Visitor david.s
Visitor
1,513 Views
Registered: ‎01-05-2018

PHY not detected PS EMIO using xapp1305

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I'm following the Wiki instructions in section 2.4 to set up PS-EMIO-1000BASE-X and I am getting a PHY is not detected.

 

U-Boot 2017.01 (Jul 19 2018 - 13:33:00 -0700) Xilinx ZynqMP ZCU102 revB

I2C:   ready
DRAM:  4 GiB
EL Level:       EL2
Chip ID:        xczu9eg
MMC:   sdhci@ff170000: 0 (SD)
reading uboot.env

** Unable to read "uboot.env" from mmc0:1 **
Using default environment

In:    serial
Out:   serial
Err:   serial
Bootmode: LVL_SHFT_SD_MODE1
Net:   ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
PHY is not detected
GEM PHY init failed
No ethernet found.
U-BOOT for david_petalinux

ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
No ethernet found.
ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'

To elaborate. I am building from the hdf that I generate from the Vivado project, not using the bsp. I create the Petalinux project, configure the kernel and then modify the system-user.dtsi as written in section 2.4.1.5. However, when I boot from SD card with the generated image.ub and BOOT.BIN, I see the message above. I have tried this flow multiple times and I am thinking that either I am missing a step, or the instructions are incomplete. Can anyone replicate this flow, or provide some suggestions?

 

Thanks

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1 Solution

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Visitor david.s
Visitor
1,456 Views
Registered: ‎01-05-2018

Re: PHY not detected PS EMIO using xapp1305

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I've figured out a work around now. I removed the i2c node from system-user.dtsi and changed the 1G/2.5G IP in the example design to use a 156.25MHz refclk. The Si570 defaults to this frequency and there seems to be an issue with trying to patch it to run at 125MHz like the Xilinx wiki instructs. 

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8 Replies
Visitor david.s
Visitor
1,455 Views
Registered: ‎01-05-2018

Re: PHY not detected PS EMIO using xapp1305

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According to this comment, U-boot and 2017.3 will not work with the instructions provided in xapp1305. I've since upgraded Petalinux to 2018.2 and have a different message in the U-boot console.

 

U-Boot 2018.01 (Jul 20 2018 - 16:17:42 -0700) Xilinx ZynqMP ZCU102 rev1.0

I2C:   ready
DRAM:  4 GiB
EL Level:       EL2
Chip ID:        zu9eg
MMC:   sdhci@ff170000: 0 (SD)
*** Warning - bad CRC, using default environment

In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Board: Xilinx ZynqMP
Bootmode: LVL_SHFT_SD_MODE1
Net:   ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
Could not get PHY for eth0: addr 9
No ethernet found.
U-BOOT for david_petalinux

ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
No ethernet found.
ZYNQ GEM: ff0b0000, phyaddr 9, interface gmii
mdio_register: non unique device name 'eth0'
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Moderator
Moderator
1,431 Views
Registered: ‎12-04-2016

Re: PHY not detected PS EMIO using xapp1305

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Hi

 

Try adding this device tree node to system-user.dtsi

 

ethernet@ff0b0000 {

      phy-handle = <&phy0>;

      is-internal-pcspma;

phy0: phy@1 {

          compatible = "marvell, 88E1518";
          device-type = "ethernet-phy";
          reg = <1>;
       };
};  

                            

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Visitor david.s
Visitor
1,416 Views
Registered: ‎01-05-2018

Re: PHY not detected PS EMIO using xapp1305

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Hi there

 

I've replaced the &gem0 node with the one you provided and I see no difference. I also noticed that the LED status lights on the ZCU102 (defined in the xdc) are not toggling. I'm now wondering if the core is actually getting the gtrefclk from the Si570?

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Visitor david.s
Visitor
1,457 Views
Registered: ‎01-05-2018

Re: PHY not detected PS EMIO using xapp1305

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I've figured out a work around now. I removed the i2c node from system-user.dtsi and changed the 1G/2.5G IP in the example design to use a 156.25MHz refclk. The Si570 defaults to this frequency and there seems to be an issue with trying to patch it to run at 125MHz like the Xilinx wiki instructs. 

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Explorer
Explorer
1,254 Views
Registered: ‎11-05-2008

Re: PHY not detected PS EMIO using xapp1305

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Hi @shabbirk,

 

  this setting in device-tree give me a syntax error.

 

Luca

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Explorer
Explorer
1,253 Views
Registered: ‎11-05-2008

Re: PHY not detected PS EMIO using xapp1305

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Hi @david.s,

 

   I have followed your suggestion. I confirm that si570 reference clock is kept to default 156.25 MHz with zcu 2018.2 bsp flow.

 

   But I cannot make ethenet come up right. I get the following message in U-BOOT:

 

   ethernet@ff0b0000 Waiting for PHY auto negotiation to complete......................................... TIMEOUT !

 

   Where can I search for a possible cause?

 

Thanks,

Luca

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Explorer
Explorer
1,234 Views
Registered: ‎11-05-2008

Re: PHY not detected PS EMIO using xapp1305

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This is my user device-tree

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Visitor david.s
Visitor
1,219 Views
Registered: ‎01-05-2018

Re: PHY not detected PS EMIO using xapp1305

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Hi luca,

 

Your device tree looks fine. Have you confirmed your clocks to the pcs/pma core? Make sure the frequencies are correct for gtrefclk and independent_clock_bufg.

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