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phypower-mengyang
Contributor
Contributor
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Registered: ‎09-04-2018

PL accessing PS DDR is slow under linux than SDK

Hi all

We have a SoC design with an 'axi datamover' in the PL interfaced to the S_AXI_HP0_FPD port of the Zynq(ZU11EG)

the PS DDR4 Configuration:   4GB / 2400P

AXI_HP0_FPD Configuration:  125MHz * 128bit

CASE1: under linux

PL send 16KB package to PS DDR(high 2G mem address),  the performance is about 400MB, we use ILA to capture the AXI_HP0_FPD port,  and find that the ‘axi_wready’ sometime go to '0'

CASE2: SDK

PL send 16KB package to PS DDR(high 2G mem address),  the performance is about1900MB, we use ILA to capture the AXI_HP0_FPD port,  and find that the ‘axi_wready’ is always  '1'

CASE3: only run uboot not load linux image

PL send 16KB package to PS DDR(high 2G mem address),  the performance is about1900MB, we use ILA to capture the AXI_HP0_FPD port,  and find that the ‘axi_wready’ is always  '1'

 

it seem that after load linux image, the PL to PS DMA performance has been restrict

Is anyone ever had the same situation? How to speed up under linux?  Thanks

 

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florentw
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Moderator
108 Views
Registered: ‎11-09-2015

Hi @phypower-mengyang 

This is expected to have lower performance under linux because the linux OS is managing the memory and creates an overhead.

You might be able to mitigate this by looking at the QoS settings for the DDR controller in the ZU+ TRM UG1085. You can reduce the priority of the OS to the DDR controller and increase the one for the PL


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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