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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

PL interrupts in Linux

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Is there any general guide to build petalinux for Zynq Us+ with interrupts from PL?

I followed this: Testing UIO with Interrupt on Zynq Ultrascale but didn't work me (error at build).

I think the reason is I don't have an AXI block to generate the interrupt but a counter from a clock. I suppose that is a valid interrupt source.

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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

 went back to this problem and found a solution here:

https://forums.xilinx.com/t5/Embedded-Linux/PL-PS-INTERRUPT-on-Ultrazed-on-Petalinux/td-p/925019

And it seems that the right inclusion in the dtsi is:

/include/ "system-conf.dtsi"
/ {
    chosen {
        bootargs = "earlycon clk_ignore_unused   uio_pdrv_genirq.of_id=generic-uio";
        stdout-path = "serial0:115200n8";
    };
};
  
&<your_hw_ip> {
    compatible = "generic-uio";
};

 

Where <your_hw_ip> is the name of the IP block in Vivado.

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@joancab 

Does your interrupt driver pin from the PL to the PS have the appropriate properties attached?

  • CONFIG.SENSITIVITY = LEVEL_HIGH, LEVEL_LOW, EDGE_FALLING, or EDGE_RISING
  • TYPE = intr

If you have multiple interrupts, you will want to use the "concat" block to concatenate these and this IP will pass the properties appropriately on the output.

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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

I expected these properties to affect the interrupt input, not the source.

Anyways, my source is a Verilog file dragged to a block diagram, the pin property is 'undef' and not editable in the Properties tab, is that something to set in the verilog file?

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@joancab 

Here is a quick example I put together when you drive an interrupt (not defined as interrupt in block diagram) and the output applies the CONFIG:SENSITIVITY and TYPE properly.

`timescale 1ns / 1ps

module myIntr (
  input  INTR_IN,
  (* X_INTERFACE_INFO = "XIL_INTERFACENAME INTR_OUT, SENSITIVITY LEVEL_HIGH, PortWidth 1" *)
  (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 INTR_OUT INTERRUPT" *)
   output INTR_OUT
);

assign INTR_OUT = INTR_IN;

endmodule
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joancab
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Registered: ‎05-11-2015

I was having a look at the AXI interrupt controller that seems to do that 'conversion' but that looks simpler. I'll give it a go.

First time I see these "directives", I noticed there is a lot in the templates window, good to know.

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joancab
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Registered: ‎05-11-2015

That seems to, at least, allow petalinux to build. Next step is the device tree, because I'm not using any AXI peripheral, I added a node (int0) in system-user.dtsi:

/include/ "system-conf.dtsi"
/ {
    chosen {
        bootargs = "earlycon clk_ignore_unused   uio_pdrv_genirq.of_id=generic-uio";
        stdout-path = "serial0:115200n8";
    };

	plinterrupt@0{
		interrupt-parent = <&gic>;
		interrupts = <0 112 1>;
	};
};

After build and boot, I expected to see the interrupt listed by    cat /proc/interrupts, but that doesn't happen.

 

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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

 went back to this problem and found a solution here:

https://forums.xilinx.com/t5/Embedded-Linux/PL-PS-INTERRUPT-on-Ultrazed-on-Petalinux/td-p/925019

And it seems that the right inclusion in the dtsi is:

/include/ "system-conf.dtsi"
/ {
    chosen {
        bootargs = "earlycon clk_ignore_unused   uio_pdrv_genirq.of_id=generic-uio";
        stdout-path = "serial0:115200n8";
    };
};
  
&<your_hw_ip> {
    compatible = "generic-uio";
};

 

Where <your_hw_ip> is the name of the IP block in Vivado.

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