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clivewmwalker
Explorer
Explorer
290 Views
Registered: ‎03-21-2013

PL reprogramming (Linux)

I’m starting to look at reloading the PL for different purposes, without restarting Linux on our product's Zynq Ultrascale+ MPSoC. I am totally new to this process.

In principle, this is what I am trying to achieve:

  • Customer has our product, which could be configured with one of 2 FPGA PL bitstreams: PL1 and PL2
  • Initially, by default, the product is configured with PL1.
  • The user suddenly makes a selection which requires PL2.
  • Without restarting Linux, the PL must be reloaded from PL1 to PL2

Can someone give me the basic principles behind the process I might need to follow to achieve this? Links to the process documentation gratefully received.

After a small amount of googling, and looking through Xilinx wiki pages etc, I sort of conclude (I could be wrong) that this process requires the use of the FPGA manager – which I am looking into. I am also aware that it might involve the usage of partial FPGA reconfiguration, which scares me somewhat. Am I correct? I also see Device Tree Overlays being mentioned quite a lot.

I'm particularly interested in those who have managed to achieve this, and/or Xilinx folks who have worked on this process.

I will keep reading.

Thanks

 

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3 Replies
watari
Professor
Professor
199 Views
Registered: ‎06-16-2013

Hi @clivewmwalker 

 

>After a small amount of googling, and looking through Xilinx wiki pages etc, I sort of conclude (I could be wrong) that this process requires the use of the FPGA manager – which I am looking into. I am also aware that it might involve the usage of partial FPGA reconfiguration, which scares me somewhat. Am I correct?

 

Yes.

FPGA manager reload FPGA bit stream to reconfigure it with device tree overlay technology.

Also, you have to understand DFX, too.

Would you refer it ?

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug947-vivado-partial-reconfiguration-tutorial.pdf

 

Best regards,

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jrhtech
Voyager
Voyager
146 Views
Registered: ‎10-04-2017

You do not have to do partial configuration or overlays if two FPGA images have similar interfaces.   I do this all the time during debug, I just use FPGA-util to reload the PL.

  This could work for multiple bitstreams depending on the design.

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aravindb
Moderator
Moderator
118 Views
Registered: ‎02-07-2018

Hi @clivewmwalker 

Yes, It is possible to load he 2nd PL bitstream once the Linux is booted. 

Please refer this section for more info: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug1144-petalinux-tools-reference-guide.pdf (FPGA Manager Configuration and Usage for Zynq-7000 Devices and Zynq UltraScale+ MPSoC)

Note:. It is mandatory that  multiple bitstreams are designed  for same PS only and the corresponding dtbos have to be packed into the root file system

 

Thanks & Regards

Aravind

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