UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor swordfishman
Visitor
5,153 Views
Registered: ‎05-29-2013

PL to PS interrupts fail to fire

I have a custom kernel module that is configured to read a particular IRQ when driven by PL via the F2P.  I can fire this interrupt by manually setting the status pending bit (register 0xf8f0120[4,8] but I never see an interrupt from fabric (PL).  A core has convinced me that the F2P line is being set and I believe it is being routed to the GIC.

 

I am concerned that there is something I am missing WRT the GIC configuration.  The environment is rather clug-ie in that this is targeting a DRS Picoflexor that requires my firmware engineer to build his project in ISE14.1 and then integrate the subsequent netlist into an Eclipse based nightmare written by IVEIA to generate a bit.

 

In order to reduce the scope of the investigation I moved my design to a ZC706 (zynq 7045) where I have confirmed the same issue.  I have done this previously in a planAhead project with success but the new project is written in Vivado and doesn't show the IRQ mapping the way I am have previously expernienced in XPS.

 

I have experimented with IRQs 91:84 and 67:60.  

 

I would most like to know of a register I can peek in the GIC to confirm that the F2P is actually being routed.

 

Any ideas on how to proceed are appreciated.

Tags (4)
0 Kudos
1 Reply
Visitor swordfishman
Visitor
5,116 Views
Registered: ‎05-29-2013

Re: PL to PS interrupts fail to fire

Just a follow-up.  The problem was that the IVEIA code mapped multiple wires to a single IRQ(91) which looked as though they were only using a single IRQ but were infact using 5.  As such our additions to the F2P BUS were offset by 4 bits from where it appeared that they should be.

 

The good news is we now have interrupts operating.

 

Cheers,

Benjamin Shaw Davis

0 Kudos