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lch
Visitor
Visitor
157 Views
Registered: ‎06-07-2021

PS_ SRST_ B

Hi All,

      "PS_SRST_B System reset commonly used during debug to reset the PS. By default, but
optional, tri-stating of the PL I/O and clearing of the PL configuration begins at the de-assertion of the PS_SRST_B signal"    

     From the above description of Zynq UltraScale+ Device TRM, it seems that PS_ SRST_ B may not reset PL, but Xilinx documents do not specify how to do it and whether there are other conditions.

     Please kindly tell me to how to not reset PL by PS_SRST_B pin.

Thanks!

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abhinayp
Xilinx Employee
Xilinx Employee
76 Views
Registered: ‎07-12-2018

Hi @lch ,

 

We have concept call PS only reset where PL remains functional. Below is the link attached and it has the Linux commands info, please have a look.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841820/Zynq+UltraScale+MPSoC+Restart+solution#ZynqUltraScale%2BMPSoCRestartsolution-PS-OnlyReset

 

Best Regards
Abhinay PS
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